top5_rx_3s250e_pq208_tr_a.ucf

XAPP485 - 以高达 666 Mbps 的速率在 Spartan-3E FPGA 中实现 1：7 的解串行化

# November 1st 2006
#
# Timespec should be set to period plus an amount for jitter
# For example : pixel clock of 90 MHz => high speed clock of 315 MHz (3175 pS).
# 		From spreadsheet : jitter is 464 pS
# 		1/(3175 - (0.5*464)) => 340 MHz

net rxclk35 tnm = rxclk35 ;
net rxclk35not tnm = rxclk35not ;
net rxclk tnm = rxclk1 ;

timespec tsrx00 = period rxclk35 340 Mhz ;
timespec tsrx01 = period rxclk35not tsrx00 ;
timespec tsrx02 = period rxclk1 tsrx00/3.5 ;
timespec tsrx03 = from rxclk35 to rxclk1 = tsrx00/2 ;

# receive clock input 1, bank 0

net "rxclkina1_p" loc = "P180" ;		# IO_L08_P_0/GCLK6
net "rxclkina1_n" loc = "P181" ;		# IO_L08_N_0/GCLK7

# channel A lvds inputs - Bank 0

net "dataina_p(0)"	loc = "P177" ;		# IO_L07_P/GCLK4
net "dataina_n(0)"	loc = "P178" ;		# IO_L07_N/GCLK5
net "dataina_p(1)"	loc = "P171" ;		# IO_L05_P
net "dataina_n(1)"	loc = "P172" ;		# IO_L05_N
net "dataina_p(2)"	loc = "P167" ;		# IO_L04_P
net "dataina_n(2)"	loc = "P168"  ;		# IO_L04_N
net "dataina_p(3)"	loc = "P164" ;		# IO_L03_P
net "dataina_n(3)"	loc = "P165" ;		# IO_L03_N
net "dataina_p(4)"	loc = "P162" ;		# IO_L02_P
net "dataina_n(4)"	loc = "P163" ;		# IO_L02_N
#net "dataina_p(5)"	loc = "P160" ;		# IO_L01_P
#net "dataina_n(5)"	loc = "P161" ;		# IO_L01_N


set "rx0/hset" rloc_origin = "X34Y60" ;

set "apa0/hset" rloc_origin = "X14Y66" ;					# Delete or comment this line if auto phase alignment is not being used

timespec tsapa00 = from ffs(apa0/chfoundc) to ffs(apa0/sm) = tsrx00/2 ;		# Delete or comment this line if auto phase alignment is not being used