top5_rx_3s500e_ft256_tr_a.ucf

来自「XAPP485 - 以高达 666 Mbps 的速率在 Spartan-3E F」· UCF 代码 · 共 42 行

# November 1st 2006
#
# Timespec should be set to period plus an amount for jitter
# For example : pixel clock of 90 MHz => high speed clock of 315 MHz (3175 pS).
# 		From spreadsheet : jitter is 464 pS
# 		1/(3175 - (0.5*464)) => 340 MHz

net rxclk35 tnm = rxclk35 ;
net rxclk35not tnm = rxclk35not ;
net rxclk tnm = rxclk1 ;

timespec tsrx00 = period rxclk35 340 Mhz ;
timespec tsrx01 = period rxclk35not tsrx00 ;
timespec tsrx02 = period rxclk1 tsrx00/3.5 ;
timespec tsrx03 = from rxclk35 to rxclk1 = tsrx00/2 ;

# receive clock input 1, bank 0

net "rxclkina1_p" loc = "A10" ;			# IO_L09_P_0/GCLK6
net "rxclkina1_n" loc = "A9" ;			# IO_L09_N_0/GCLK7

# channel A lvds inputs - Bank 0

net "dataina_p(0)"	loc = "E9" ;		# IO_L08_P
net "dataina_n(0)"	loc = "F9" ;		# IO_L08_N
net "dataina_p(1)"	loc = "D10" ;		# IO_L06_P
net "dataina_n(1)"	loc = "E10" ;		# IO_L06_N
net "dataina_p(2)"	loc = "C11" ;		# IO_L05_P
net "dataina_n(2)"	loc = "B11"  ;		# IO_L05_N
net "dataina_p(3)"	loc = "D11" ;		# IO_L04_P
net "dataina_n(3)"	loc = "E11" ;		# IO_L04_N
net "dataina_p(4)"	loc = "B13" ;		# IO_L03_P
net "dataina_n(4)"	loc = "A13" ;		# IO_L03_N
#net "dataina_p(5)"	loc = "B14" ;		# IO_L01_P
#net "dataina_n(5)"	loc = "A14" ;		# IO_L01_N

set "rx0/hset" rloc_origin = "X42Y84" ;

set "apa0/hset" rloc_origin = "X50Y90" ;					# Delete or comment this line if auto phase alignment is not being used

timespec tsapa00 = from ffs(apa0/chfoundc) to ffs(apa0/sm) = tsrx00/2 ;		# Delete or comment this line if auto phase alignment is not being used