auto_phase_align_s3e.vhd

XAPP485 - 以高达 666 Mbps 的速率在 Spartan-3E FPGA 中实现 1：7 的解串行化

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--  Xilinx, Inc. 2006                 www.xilinx.com
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--  XAPP 485 - 1:7 LVDS in Spartan3E Devices
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--  File name :       auto_phase_align_s3e.vhd
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--  Description :     Automatic phase aligner, Note counters are long enough (13-bit)
--			for operation down to 5 MHz assuming 25 pS per tap. (200,000/25=8,000)
--			Spartan 3E version (DCM is different from Spartan3)
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--  Date - revision : 11th November 2006 - v 1.1
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--  Author :          NJS
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