📄 single_send.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY single_send IS
PORT (
in_data :IN STD_LOGIC;
in_clk :IN STD_LOGIC;
out_data :OUT std_logic;
out_clk :OUT std_logic
);
END single_send;
ARCHITECTURE A OF single_send IS
-- SIGNAL send_counter : std_logic_vector(1 downto 0);
SIGNAL send_counter : std_logic;
--SIGNAL ldd_clk : STD_LOGIC;
-- SIGNAL rclk : STD_LOGIC;
SIGNAL data_temp : STD_LOGIC;
BEGIN
out_clk<=in_clk;
send_data: process (in_clk)
begin
if in_clk'event and in_clk='1' then
if send_counter='0' then
data_temp<=in_data;
out_data<=data_temp;
send_counter<='1';
elsif send_counter='1' then
out_data<=not data_temp;
-- if in_data/=data_temp then
-- send_counter<='1';
-- out_data<= data_temp;
-- else
send_counter<='0';
-- out_data<=not data_temp;
-- end if;
else
send_counter<='0';
end if ;
end if;
end process send_data;
END ;
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