test.rpt

上海外滩看到的最大的LED显示屏的内核源代码

 (29)    41    C       TFFE   +  t        0      0   0    0    0    0    2  |SINGLE_SEND:24|send_counter (|SINGLE_SEND:24|:6)
   -      9    A       DFFE   +  t        0      0   0    1    2    0    2  |SINGLE_SEND:24|data_temp (|SINGLE_SEND:24|:7)
   -      6    A       DFFE   +  t        0      0   0    0    2    0    2  |SINGLE_SEND:35|:3
   -     34    C       TFFE   +  t        0      0   0    0    0    0    2  |SINGLE_SEND:35|send_counter (|SINGLE_SEND:35|:6)
  (9)     4    A       DFFE   +  t        0      0   0    1    2    0    2  |SINGLE_SEND:35|data_temp (|SINGLE_SEND:35|:7)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                           d:\cpld(huaqi)\test.rpt
test

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                 Logic cells placed in LAB 'A'
        +------- LC10 |SINGLE_SEND:24|:3
        | +----- LC9 |SINGLE_SEND:24|data_temp
        | | +--- LC6 |SINGLE_SEND:35|:3
        | | | +- LC4 |SINGLE_SEND:35|data_temp
        | | | | 
        | | | |   Other LABs fed by signals
        | | | |   that feed LAB 'A'
LC      | | | | | A B C D |     Logic cells that feed LAB 'A':
LC9  -> * * - - | * - - - | <-- |SINGLE_SEND:24|data_temp
LC4  -> - - * * | * - - - | <-- |SINGLE_SEND:35|data_temp

Pin
43   -> - - - - | - - - - | <-- in_clk
4    -> - - - * | * - - - | <-- lat_data
8    -> - * - - | * - - - | <-- oe_data
LC41 -> * * - - | * - - - | <-- |SINGLE_SEND:24|send_counter
LC34 -> - - * * | * - - - | <-- |SINGLE_SEND:35|send_counter


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           d:\cpld(huaqi)\test.rpt
test

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                         Logic cells placed in LAB 'B'
        +------------------------------- LC22 |LDD_SEND:39|rclk1
        | +----------------------------- LC18 |LDD_SEND:39|rclk3
        | | +--------------------------- LC17 out_b
        | | | +------------------------- LC20 out_g
        | | | | +----------------------- LC21 out_oe
        | | | | | +--------------------- LC25 out_r
        | | | | | | +------------------- LC28 |SINGLE_RECEIVE:21|t0_in_r
        | | | | | | | +----------------- LC27 |SINGLE_RECEIVE:21|t1_in_r
        | | | | | | | | +--------------- LC24 |SINGLE_RECEIVE:22|t0_in_r
        | | | | | | | | | +------------- LC23 |SINGLE_RECEIVE:22|t1_in_r
        | | | | | | | | | | +----------- LC19 |SINGLE_SEND:1|:3
        | | | | | | | | | | | +--------- LC26 |SINGLE_SEND:1|data_temp
        | | | | | | | | | | | | +------- LC29 |SINGLE_SEND:12|:3
        | | | | | | | | | | | | | +----- LC32 |SINGLE_SEND:12|data_temp
        | | | | | | | | | | | | | | +--- LC31 |SINGLE_SEND:23|:3
        | | | | | | | | | | | | | | | +- LC30 |SINGLE_SEND:23|data_temp
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'B':
LC17 -> - - * - - - - - - - - - - - - - | - * - - | <-- out_b
LC20 -> - - - * - - - - - - - - - - - - | - * - - | <-- out_g
LC21 -> - - - - * - - - - - - - - - - - | - * - - | <-- out_oe
LC25 -> - - - - - * - - - - - - - - - - | - * - - | <-- out_r
LC28 -> - - * - - - - - - - - - - - - - | - * - - | <-- |SINGLE_RECEIVE:21|t0_in_r
LC27 -> - - * - - - - - - - - - - - - - | - * - - | <-- |SINGLE_RECEIVE:21|t1_in_r
LC24 -> - - - - * - - - - - - - - - - - | - * - - | <-- |SINGLE_RECEIVE:22|t0_in_r
LC23 -> - - - - * - - - - - - - - - - - | - * - - | <-- |SINGLE_RECEIVE:22|t1_in_r
LC26 -> - - - - - - - - - - * * - - - - | - * - - | <-- |SINGLE_SEND:1|data_temp
LC32 -> - - - - - - - - - - - - * * - - | - * - - | <-- |SINGLE_SEND:12|data_temp
LC31 -> - - - - - - * * - - - - - - - - | - * - - | <-- |SINGLE_SEND:23|:3
LC30 -> - - - - - - - - - - - - - - * * | - * - - | <-- |SINGLE_SEND:23|data_temp

Pin
11   -> - - - - - - - - - - - - - - - * | - * - - | <-- b_data
6    -> * - - - - - - - - - - - - - - - | - * - - | <-- clk50M
5    -> - - - - - - - - - - - - - * - - | - * - - | <-- g_data
43   -> - - - - - - - - - - - - - - - - | - - - - | <-- in_clk
12   -> - - - - - - - - - - - * - - - - | - * - - | <-- r_data
LC63 -> - * - - - - - - - - - - - - - - | - * - - | <-- |LDD_SEND:39|rclk2
LC33 -> - - * * * * * * * * - - - - - - | - * * - | <-- out_rclk
LC48 -> - - - - - * - - - - - - - - - - | - * - - | <-- |SINGLE_RECEIVE:2|t0_in_r
LC45 -> - - - - - * - - - - - - - - - - | - * - - | <-- |SINGLE_RECEIVE:2|t1_in_r
LC36 -> - - - * - - - - - - - - - - - - | - * - - | <-- |SINGLE_RECEIVE:11|t0_in_r
LC44 -> - - - * - - - - - - - - - - - - | - * - - | <-- |SINGLE_RECEIVE:11|t1_in_r
LC64 -> - - - - - - - - - - * * - - - - | - * - - | <-- |SINGLE_SEND:1|send_counter
LC51 -> - - - - - - - - - - - - * * - - | - * - - | <-- |SINGLE_SEND:12|send_counter
LC58 -> - - - - - - - - - - - - - - * * | - * - - | <-- |SINGLE_SEND:23|send_counter
LC10 -> - - - - - - - - * * - - - - - - | - * - - | <-- |SINGLE_SEND:24|:3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           d:\cpld(huaqi)\test.rpt
test

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                                         Logic cells placed in LAB 'C'
        +------------------------------- LC47 |LAT_RECEIVE:37|LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node1
        | +----------------------------- LC46 |LAT_RECEIVE:37|LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node2
        | | +--------------------------- LC43 |LAT_RECEIVE:37|count3
        | | | +------------------------- LC42 |LAT_RECEIVE:37|count2
        | | | | +----------------------- LC37 |LAT_RECEIVE:37|count1
        | | | | | +--------------------- LC38 |LAT_RECEIVE:37|count0
        | | | | | | +------------------- LC39 |LAT_RECEIVE:37|t0_in_lat
        | | | | | | | +----------------- LC40 |LAT_RECEIVE:37|t1_in_lat
        | | | | | | | | +--------------- LC35 out_lat
        | | | | | | | | | +------------- LC33 out_rclk
        | | | | | | | | | | +----------- LC48 |SINGLE_RECEIVE:2|t0_in_r
        | | | | | | | | | | | +--------- LC45 |SINGLE_RECEIVE:2|t1_in_r
        | | | | | | | | | | | | +------- LC36 |SINGLE_RECEIVE:11|t0_in_r
        | | | | | | | | | | | | | +----- LC44 |SINGLE_RECEIVE:11|t1_in_r
        | | | | | | | | | | | | | | +--- LC41 |SINGLE_SEND:24|send_counter
        | | | | | | | | | | | | | | | +- LC34 |SINGLE_SEND:35|send_counter
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'C':
LC47 -> - - - - * - - - - - - - - - - - | - - * - | <-- |LAT_RECEIVE:37|LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node1
LC46 -> - - - * - - - - - - - - - - - - | - - * - | <-- |LAT_RECEIVE:37|LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node2
LC43 -> - - * * * * - - - * - - - - - - | - - * - | <-- |LAT_RECEIVE:37|count3
LC42 -> - * * * * * - - - * - - - - - - | - - * - | <-- |LAT_RECEIVE:37|count2
LC37 -> * * * - - - - - - * - - - - - - | - - * - | <-- |LAT_RECEIVE:37|count1
LC38 -> * * * - - * - - - * - - - - - - | - - * - | <-- |LAT_RECEIVE:37|count0
LC39 -> - - - - - - - - * - - - - - - - | - - * - | <-- |LAT_RECEIVE:37|t0_in_lat
LC40 -> - - - - - - - - * - - - - - - - | - - * - | <-- |LAT_RECEIVE:37|t1_in_lat
LC35 -> - - * * * * - - * - - - - - - - | - - * - | <-- out_lat
LC33 -> - - - - - - * * * * * * * * - - | - * * - | <-- out_rclk

Pin
43   -> - - - - - - - - - - - - - - - - | - - - - | <-- in_clk
LC19 -> - - - - - - - - - - * * - - - - | - - * - | <-- |SINGLE_SEND:1|:3
LC29 -> - - - - - - - - - - - - * * - - | - - * - | <-- |SINGLE_SEND:12|:3
LC6  -> - - - - - - * * - - - - - - - - | - - * - | <-- |SINGLE_SEND:35|:3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           d:\cpld(huaqi)\test.rpt
test

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                         Logic cells placed in LAB 'D'
        +------------------------------- LC53 |LDD_RECEIVE:38|count10
        | +----------------------------- LC54 |LDD_RECEIVE:38|count9
        | | +--------------------------- LC55 |LDD_RECEIVE:38|count8
        | | | +------------------------- LC56 |LDD_RECEIVE:38|count7
        | | | | +----------------------- LC60 |LDD_RECEIVE:38|count6
        | | | | | +--------------------- LC62 |LDD_RECEIVE:38|count5
        | | | | | | +------------------- LC61 |LDD_RECEIVE:38|count4
        | | | | | | | +----------------- LC59 |LDD_RECEIVE:38|count3
        | | | | | | | | +--------------- LC57 |LDD_RECEIVE:38|count2
        | | | | | | | | | +------------- LC52 |LDD_RECEIVE:38|count1
        | | | | | | | | | | +----------- LC50 |LDD_RECEIVE:38|count0
        | | | | | | | | | | | +--------- LC63 |LDD_SEND:39|rclk2
        | | | | | | | | | | | | +------- LC49 out_ldd
        | | | | | | | | | | | | | +----- LC64 |SINGLE_SEND:1|send_counter
        | | | | | | | | | | | | | | +--- LC51 |SINGLE_SEND:12|send_counter
        | | | | | | | | | | | | | | | +- LC58 |SINGLE_SEND:23|send_counter
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':
LC53 -> * - - - - - - - - - - - * - - - | - - - * | <-- |LDD_RECEIVE:38|count10
LC54 -> * * - - - - - - - - - - * - - - | - - - * | <-- |LDD_RECEIVE:38|count9
LC55 -> * * * - - - - - - - - - * - - - | - - - * | <-- |LDD_RECEIVE:38|count8
LC56 -> * * * * - - - - - - - - * - - - | - - - * | <-- |LDD_RECEIVE:38|count7
LC60 -> * * * * * - - - - - - - * - - - | - - - * | <-- |LDD_RECEIVE:38|count6
LC62 -> * * * * * * - - - - - - * - - - | - - - * | <-- |LDD_RECEIVE:38|count5
LC61 -> * * * * * * * - - - - - * - - - | - - - * | <-- |LDD_RECEIVE:38|count4
LC59 -> * * * * * * * * - - - - * - - - | - - - * | <-- |LDD_RECEIVE:38|count3
LC57 -> * * * * * * * * * - - - * - - - | - - - * | <-- |LDD_RECEIVE:38|count2
LC52 -> * * * * * * * * * * - - * - - - | - - - * | <-- |LDD_RECEIVE:38|count1
LC50 -> * * * * * * * * * * * - - - - - | - - - * | <-- |LDD_RECEIVE:38|count0

Pin
43   -> - - - - - - - - - - - - - - - - | - - - - | <-- in_clk
9    -> * * * * * * * * * * * - - - - - | - - - * | <-- ldd_data
LC22 -> * * * * * * * * * * * * - - - - | - - - * | <-- |LDD_SEND:39|rclk1
LC18 -> * * * * * * * * * * * - - - - - | - - - * | <-- |LDD_SEND:39|rclk3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           d:\cpld(huaqi)\test.rpt
test

** EQUATIONS **

b_data   : INPUT;
clk50M   : INPUT;
g_data   : INPUT;
in_clk   : INPUT;
lat_data : INPUT;
ldd_data : INPUT;
oe_data  : INPUT;
r_data   : INPUT;

-- Node name is 'out_b' = '|SINGLE_RECEIVE:21|:3' 
-- Equation name is 'out_b', type is output 
 out_b   = DFFE( _EQ001 $  _LC028, !out_rclk,  VCC,  VCC,  VCC);
  _EQ001 =  _LC027 &  _LC028 & !out_b
         # !_LC027 & !_LC028 &  out_b;

-- Node name is 'out_g' = '|SINGLE_RECEIVE:11|:3' 
-- Equation name is 'out_g', type is output 
 out_g   = DFFE( _EQ002 $  _LC036, !out_rclk,  VCC,  VCC,  VCC);
  _EQ002 =  _LC036 &  _LC044 & !out_g
         # !_LC036 & !_LC044 &  out_g;

-- Node name is 'out_lat' = '|LAT_RECEIVE:37|lat_temp' 
-- Equation name is 'out_lat', type is output 
 out_lat = DFFE( _EQ003 $  _LC039, !out_rclk,  VCC,  VCC,  VCC);
  _EQ003 =  _LC039 &  _LC040 & !out_lat
         # !_LC039 & !_LC040 &  out_lat;

-- Node name is 'out_ldd' 
-- Equation name is 'out_ldd', location is LC049, type is output.
 out_ldd = LCELL( _EQ004 $  VCC);
  _EQ004 = !_LC052 & !_LC053 & !_LC054 & !_LC055 & !_LC056 & !_LC057 & 
             !_LC059 & !_LC060 & !_LC061 & !_LC062;

-- Node name is 'out_oe' = '|SINGLE_RECEIVE:22|:3' 
-- Equation name is 'out_oe', type is output 
 out_oe  = DFFE( _EQ005 $  _LC024, !out_rclk,  VCC,  VCC,  VCC);
  _EQ005 =  _LC023 &  _LC024 & !out_oe
         # !_LC023 & !_LC024 &  out_oe;

-- Node name is 'out_r' = '|SINGLE_RECEIVE:2|:3' 
-- Equation name is 'out_r', type is output 
 out_r   = DFFE( _EQ006 $  _LC048, !out_rclk,  VCC,  VCC,  VCC);
  _EQ006 =  _LC045 &  _LC048 & !out_r
         # !_LC045 & !_LC048 &  out_r;

-- Node name is 'out_rclk' = '|LAT_RECEIVE:37|rclk' 
-- Equation name is 'out_rclk', type is output 
 out_rclk = DFFE( _EQ007 $  _EQ008, GLOBAL(!in_clk),  VCC,  VCC,  VCC);
  _EQ007 =  _LC038 &  _LC042 &  _LC043 & !out_rclk
         #  _LC037 &  _LC043 & !out_rclk &  _X001;
  _X001  = EXP(!_LC038 & !_LC042);
  _EQ008 =  _X002 &  _X003 &  _X004 &  _X005;
  _X002  = EXP(!_LC037 & !_LC042 &  out_rclk);
  _X003  = EXP(!_LC038 & !_LC042 &  out_rclk);
  _X004  = EXP(!_LC037 & !_LC038 &  out_rclk);
  _X005  = EXP(!_LC043 &  out_rclk);

-- Node name is '|LAT_RECEIVE:37|:15' = '|LAT_RECEIVE:37|count0' 
-- Equation name is '_LC038', type is buried 
_LC038   = DFFE( _EQ009 $  GND, GLOBAL( in_clk),  out_lat,  VCC,  VCC);
  _EQ009 = !_LC038 & !_LC042 &  _LC043
         # !_LC038 & !_LC043;

-- Node name is '|LAT_RECEIVE:37|:14' = '|LAT_RECEIVE:37|count1' 
-- Equation name is '_LC037', type is buried 
_LC037   = DFFE( _EQ010 $  GND, GLOBAL( in_clk),  out_lat,  VCC,  VCC);
  _EQ010 = !_LC042 &  _LC043 &  _LC047
         # !_LC043 &  _LC047;

-- Node name is '|LAT_RECEIVE:37|:13' = '|LAT_RECEIVE:37|count2' 
-- Equation name is '_LC042', type is buried 
_LC042   = DFFE( _EQ011 $  GND, GLOBAL( in_clk),  out_lat,  VCC,  VCC);
  _EQ011 = !_LC042 &  _LC043 &  _LC046
         # !_LC043 &  _LC046;

-- Node name is '|LAT_RECEIVE:37|:12' = '|LAT_RECEIVE:37|count3' 
-- Equation name is '_LC043', type is buried 
_LC043   = DFFE( _EQ012 $  GND, GLOBAL( in_clk),  out_lat,  VCC,  VCC);
  _EQ012 =  _LC037 &  _LC038 &  _LC042 & !_LC043
         # !_LC042 &  _LC043 &  _X006;
  _X006  = EXP( _LC037 &  _LC038 &  _LC042);

-- Node name is '|LAT_RECEIVE:37|LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC047', type is buried 
_LC047   = LCELL( _LC037 $  _LC038);

-- Node name is '|LAT_RECEIVE:37|LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC046', type is buried 
_LC046   = LCELL( _LC042 $  _EQ013);
  _EQ013 =  _LC037 &  _LC038;

-- Node name is '|LAT_RECEIVE:37|:17' = '|LAT_RECEIVE:37|t0_in_lat' 
-- Equation name is '_LC039', type is buried