sd_cnfg.v

已经成功的FPGA 控制的SDRAM控制器代码.只要修改你需要的宽度就可以了.

// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2001 by Lattice Semiconductor Corporation
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//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
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// Revision History :
//---------------------------------------------------------------------
// Ver  | Author    | Mod. Date | Changes Made:
//---------------------------------------------------------------------
// 0.1  | tpf       | 11/25/98  | birth
// 1.0  | tpf       |  3/19/99  | Release
//---------------------------------------------------------------------

`timescale 1 ns /  100 ps

/*
This module provides an alternative to having an internal register to
load the sdram command mode values and to initiate the sdram startup
procedure.  Upon receiving the sdram_enable signal, which is assumed 
to be asynchronous to the clock, the state machine starts initiating 3
commands to the sdrams.  The first will be a precharge, the second will
be an auto refresh, the last wil be the load mode register command.
After performing these threee commands, the sdram will be functional.
*/

module sd_cnfg(	sdram_en,
				clk,
               	rst_l,
               	sdram_cycle,
                state_cntr,
               	sdram_mode_reg,
               	sdram_cmnd,
               	cmnd_cycle_req,
               	sdram_setup);

//---------------------------------------------------------------------
// inputs

input			sdram_en;
input			clk;
input			rst_l;
input	[3:0]	sdram_cycle;        // whose cycle is it
                                    // 0 = idle
                                    // 1 = command
                                    // 2 = data
                                    // 3 = refresh 
input   [3:0]   state_cntr;         // state bits 
                                   
//---------------------------------------------------------------------
// outputs

output  [11:0]	sdram_mode_reg;
output  [1:0]	sdram_cmnd;
output			cmnd_cycle_req;
output          sdram_setup;

//---------------------------------------------------------------------
// registers

reg				sdram_en1,
				sdram_en2;			// enable sync'd twice

reg		[3:0]	state;				// state bits

wire   	[11:0]  sdram_mode_reg;		// mode register

reg    	[1:0]	sdram_cmnd;			// 00 -- nop
									// 01 -- precharge all banks
									// 10 -- autorefresh
									// 11 -- load mode register 

reg             cmnd_cycle_req;		// request command cycle

reg             sdram_setup;        // setup complete

//---------------------------------------------------------------------
// mode register defines

// write mode set to single or programmed burst length -- mode bit[9]
`define prog_brst   0
`define single      1

// cas latency set to 2 or 3 -- mode bits[6:4]
`define cas_lat_2   3'b010
`define cas_lat_3   3'b011

// burst type sequential or interleaved -- mode bit[3]
`define seq         1'b0
`define int         1'b1

// burst length -- mode bits[2:0]
`define brst1       3'b000                 // 1
`define brst2       3'b001                 // 2
`define brst4       3'b010                 // 4
`define brst8       3'b011                 // 8
`define brstf       3'b111                 // full page

//---------------------------------------------------------------------
// sdram mode register assignment
// change values to whatever you need

assign sdram_mode_reg[11:10] = 2'b0;        // reserved
assign sdram_mode_reg[9]     = `prog_brst;  // write mode
assign sdram_mode_reg[8:7]   = 2'b0;        // reserved
assign sdram_mode_reg[6:4]   = `cas_lat_2;  // cas latency 2 clocks
assign sdram_mode_reg[3]     = `seq;        // sequential access
assign sdram_mode_reg[2:0]   = `brst8;      // burst of 8

//---------------------------------------------------------------------
// state assignments

parameter idle      = 4'b0000;
parameter precharge = 4'b0001;
parameter nop1      = 4'b0010;
parameter refresh1  = 4'b0011;
parameter nop2      = 4'b0100;
parameter refresh2  = 4'b0101;
parameter nop3      = 4'b0110;
parameter load_mode = 4'b0111;
parameter all_done  = 4'b1000;

//---------------------------------------------------------------------
// synchronize enable

always @(posedge clk or negedge rst_l)
	if (!rst_l) begin
		sdram_en1 <= #1 1'b0;
		sdram_en2 <= #1 1'b0;
		end
	else begin
		sdram_en1 <= #1 sdram_en;
		sdram_en2 <= #1 sdram_en1;
		end
		
//---------------------------------------------------------------------
// state machine

always @(posedge clk or negedge rst_l)
   if (!rst_l) begin
      state          <= #1 idle;
	  sdram_cmnd     <= #1 2'b00;
	  cmnd_cycle_req <= #1 1'b0;
      sdram_setup    <= #1 1'b0;
	  end

   else case (state)
   
	idle : if (sdram_en2) begin
        state          <= #1 precharge;
        sdram_cmnd     <= #1 2'b01;
		cmnd_cycle_req <= #1 1'b1;	
		sdram_setup    <= #1 1'b0;
	    end

	precharge : if (sdram_cycle[1] && state_cntr[3]) begin
	  	state          <= #1 nop1;
		sdram_cmnd     <= #1 2'b00;
		cmnd_cycle_req <= #1 1'b0;
      	sdram_setup    <= #1 1'b0;
	    end

	nop1 : begin
		state          <= #1 refresh1;
		sdram_cmnd     <= #1 2'b10;
		cmnd_cycle_req <= #1 1'b1;
		sdram_setup    <= #1 1'b0;
	    end

	refresh1 : if (sdram_cycle[1] && state_cntr[3]) begin
	  	state          <= #1 nop2;
		sdram_cmnd     <= #1 2'b00;
		cmnd_cycle_req <= #1 1'b0;
      	sdram_setup    <= #1 1'b0;
	    end
	  
	nop2 : begin
		state          <= #1 refresh2;
		sdram_cmnd     <= #1 2'b10;
		cmnd_cycle_req <= #1 1'b1;
		sdram_setup    <= #1 1'b0;
	    end

	refresh2 : if (sdram_cycle[1] && state_cntr[3]) begin
	  	state          <= #1 nop3;
		sdram_cmnd     <= #1 2'b00;
		cmnd_cycle_req <= #1 1'b0;
      	sdram_setup    <= #1 1'b0;
	    end
	  
	nop3 : begin
		state          <= #1 load_mode;
		sdram_cmnd     <= #1 2'b11;
		cmnd_cycle_req <= #1 1'b1;
		sdram_setup    <= #1 1'b0;
	    end

	load_mode : if (sdram_cycle[1] && state_cntr[2]) begin
	  	state          <= #1 all_done;
		sdram_cmnd     <= #1 2'b00;
		cmnd_cycle_req <= #1 1'b0;
      	sdram_setup    <= #1 1'b1;
	    end
	  
	all_done : begin
		state          <= #1 all_done;
		sdram_cmnd     <= #1 2'b00;
		cmnd_cycle_req <= #1 1'b0;
		sdram_setup    <= #1 1'b1;
	    end

	default : begin
      	state          <= #1 idle;
	 	sdram_cmnd     <= #1 2'b00;
	  	cmnd_cycle_req <= #1 1'b0;
	  	sdram_setup    <= #1 1'b0;
	    end

	endcase

endmodule