📄 频率计.txt
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity freq is
port (xclk,clk: in std_logic;
A0,B0,C0,D0,A1,B1,C1,D1:out std_logic;
A2,B2,C2,D2,A3,B3,C3,D3:out std_logic);
end;
architecture example of freq is
signal countb:std_logic_vector(3 downto 0);
signal count0:std_logic_vector(3 downto 0);
signal count1:std_logic_vector(3 downto 0);
signal count2:std_logic_vector(3 downto 0);
signal count3:std_logic_vector(3 downto 0);
signal en,clr,m0,m1,m2:std_logic;
begin
P1:process(xclk,en,clr)
begin
if(clr='0') then
count0<="0000";
m0<='0';
elsif((en='1') and rising_edge (xclk) ) then
if( count0="1001") then
count0<="0000";
m0<='0';
else
count0<=count0 + '1';
m0<='1';
end if;
end if;
end process P1;
P2:process(en,clr,m0)
begin
if(clr='0') then
count1<="0000";
m1<='0';
elsif((en='1') and falling_edge(m0) ) then
if( count1="1001") then
count1<="0000";
m1<='0';
else
count1<=count1 + '1';
m1<='1';
end if;
end if;
end process P2;
P3:process(en,clr,m1)
begin
if(clr='0') then
count2<="0000"; m2<='0';
elsif((en='1') and falling_edge(m1) ) then
if( count2="1001") then
count2<="0000";
m2<='0';
else
count2<=count2 + '1';
m2<='1';
end if;
end if;
end process P3;
P4:process(en,clr,m2)
begin
if(clr='0') then
count3<="0000";
elsif((en='1') and falling_edge(m2) ) then
if( count3="1001") then
count3<="0000";
else
count3<=count3 + '1';
end if;
end if;
end process P4;
P5:process(clk)
begin
if(rising_edge (clk) )then
countb<=countb+'1';
else
countb<=countb;
end if;
if (countb="0111") then
clr <= '0';
else
clr <= '1';
end if;
if (countb>"0111") then
en<='1';
else
en<='0';
end if;
end process P5;
A0<=count0(0);B0<=count0(1);C0<=count0(2);D0<=count0(3);
A1<=count1(0);B1<=count1(1);C1<=count1(2);D1<=count1(3);
A2<=count2(0);B2<=count2(1);C2<=count2(2);D2<=count2(3);
A3<=count3(0);B3<=count3(1);C3<=count3(2);D3<=count3(3);
end example;
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