keyboardtest.tan.rpt

键盘去抖动CPLD设计经过验证,可以直接用数码管显示,同时也希望大家给于新想法

; N/A   ; None              ; 33.000 ns       ; ROW_in[3] ; seven[5] ;
; N/A   ; None              ; 33.000 ns       ; ROW_in[2] ; seven[5] ;
; N/A   ; None              ; 33.000 ns       ; ROW_in[1] ; seven[4] ;
; N/A   ; None              ; 33.000 ns       ; ROW_in[0] ; seven[4] ;
; N/A   ; None              ; 33.000 ns       ; ROW_in[3] ; seven[4] ;
; N/A   ; None              ; 33.000 ns       ; ROW_in[2] ; seven[4] ;
+-------+-------------------+-----------------+-----------+----------+


+---------------------------------------------------------------------------------------+
; th                                                                                    ;
+---------------+-------------+-----------+-----------+----------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To                   ; To Clock ;
+---------------+-------------+-----------+-----------+----------------------+----------+
; N/A           ; None        ; 6.000 ns  ; ROW_in[2] ; debounce:keydeb|DEL1 ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; ROW_in[3] ; debounce:keydeb|DEL1 ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; ROW_in[0] ; debounce:keydeb|DEL1 ; CLK      ;
; N/A           ; None        ; 6.000 ns  ; ROW_in[1] ; debounce:keydeb|DEL1 ; CLK      ;
+---------------+-------------+-----------+-----------+----------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Aug 23 12:13:22 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off keyboardtest -c keyboardtest
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Info: Found combinational loop of 1 nodes
    Info: Node "keypress_det:key_select|REAL_code[3]~68"
Info: Found combinational loop of 1 nodes
    Info: Node "keypress_det:key_select|REAL_code[0]~64"
Info: Found combinational loop of 1 nodes
    Info: Node "keypress_det:key_select|REAL_code[2]~60"
Info: Found combinational loop of 1 nodes
    Info: Node "keypress_det:key_select|REAL_code[1]~56"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "cnt5:clkdiv|lpm_counter:out1_rtl_1|dffs[4]" as buffer
Info: Clock "CLK" has Internal fmax of 76.92 MHz between source register "CODE:codegen|lpm_counter:REG_rtl_0|dffs[0]" and destination register "CODE:codegen|lpm_counter:REG_rtl_0|dffs[0]" (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC39; Fanout = 12; REG Node = 'CODE:codegen|lpm_counter:REG_rtl_0|dffs[0]'
        Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC39; Fanout = 12; REG Node = 'CODE:codegen|lpm_counter:REG_rtl_0|dffs[0]'
        Info: Total cell delay = 8.000 ns ( 100.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 12; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC39; Fanout = 12; REG Node = 'CODE:codegen|lpm_counter:REG_rtl_0|dffs[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "CLK" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 12; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC39; Fanout = 12; REG Node = 'CODE:codegen|lpm_counter:REG_rtl_0|dffs[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register "debounce:keydeb|DEL1" (data pin = "ROW_in[2]", clock pin = "CLK") is 2.000 ns
    Info: + Longest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_37; Fanout = 6; PIN Node = 'ROW_in[2]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC84; Fanout = 3; REG Node = 'debounce:keydeb|DEL1'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
    Info: + Micro setup delay of destination is 4.000 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 12.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 12; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC45; Fanout = 5; REG Node = 'cnt5:clkdiv|lpm_counter:out1_rtl_1|dffs[4]'
        Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC84; Fanout = 3; REG Node = 'debounce:keydeb|DEL1'
        Info: Total cell delay = 10.000 ns ( 83.33 % )
        Info: Total interconnect delay = 2.000 ns ( 16.67 % )
Info: tco from clock "CLK" to destination pin "seven[3]" through register "debounce:keydeb|jkt:jkf|tq" is 44.000 ns
    Info: + Longest clock path from clock "CLK" to source register is 12.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 12; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC45; Fanout = 5; REG Node = 'cnt5:clkdiv|lpm_counter:out1_rtl_1|dffs[4]'
        Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC92; Fanout = 7; REG Node = 'debounce:keydeb|jkt:jkf|tq'
        Info: Total cell delay = 10.000 ns ( 83.33 % )
        Info: Total interconnect delay = 2.000 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 31.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC92; Fanout = 7; REG Node = 'debounce:keydeb|jkt:jkf|tq'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC81; Fanout = 13; COMB Node = 'keypress_det:key_select|always0~55'
        Info: 3: + IC(0.000 ns) + CELL(9.000 ns) = 18.000 ns; Loc. = LC33; Fanout = 24; COMB LOOP Node = 'keypress_det:key_select|REAL_code[3]~68'
            Info: Loc. = LC33; Node "keypress_det:key_select|REAL_code[3]~68"
        Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 27.000 ns; Loc. = LC91; Fanout = 1; COMB Node = 'sevenseg:SEVEN_DSP|WideOr3~157'
        Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 31.000 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'seven[3]'
        Info: Total cell delay = 27.000 ns ( 87.10 % )
        Info: Total interconnect delay = 4.000 ns ( 12.90 % )
Info: Longest tpd from source pin "ROW_in[1]" to destination pin "seven[3]" is 33.000 ns
    Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_36; Fanout = 5; PIN Node = 'ROW_in[1]'
    Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC81; Fanout = 13; COMB Node = 'keypress_det:key_select|always0~55'
    Info: 3: + IC(0.000 ns) + CELL(9.000 ns) = 20.000 ns; Loc. = LC33; Fanout = 24; COMB LOOP Node = 'keypress_det:key_select|REAL_code[3]~68'
        Info: Loc. = LC33; Node "keypress_det:key_select|REAL_code[3]~68"
    Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 29.000 ns; Loc. = LC91; Fanout = 1; COMB Node = 'sevenseg:SEVEN_DSP|WideOr3~157'
    Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 33.000 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'seven[3]'
    Info: Total cell delay = 29.000 ns ( 87.88 % )
    Info: Total interconnect delay = 4.000 ns ( 12.12 % )
Info: th for register "debounce:keydeb|DEL1" (data pin = "ROW_in[2]", clock pin = "CLK") is 6.000 ns
    Info: + Longest clock path from clock "CLK" to destination register is 12.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 12; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC45; Fanout = 5; REG Node = 'cnt5:clkdiv|lpm_counter:out1_rtl_1|dffs[4]'
        Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC84; Fanout = 3; REG Node = 'debounce:keydeb|DEL1'
        Info: Total cell delay = 10.000 ns ( 83.33 % )
        Info: Total interconnect delay = 2.000 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 4.000 ns
    Info: - Shortest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_37; Fanout = 6; PIN Node = 'ROW_in[2]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC84; Fanout = 3; REG Node = 'debounce:keydeb|DEL1'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Thu Aug 23 12:13:22 2007
    Info: Elapsed time: 00:00:00