cnt5.v

来自「键盘去抖动CPLD设计经过验证,可以直接用数码管显示,同时也希望大家给于新想法」· Verilog 代码 · 共 25 行

//-------------------------
//Clock divided by 32
//Filenale : cnt5.v
//-------------------------
module  cnt5
	(
		in,
		out
	);


	input	in;
	output	out;

	reg	[4:0]	out1;

always@(posedge in  )
begin
     out1<= out1 + 5'b1;  
end

assign out = out1[4];

endmodule