fengping.map.qmsg

这是一个用VHDL语言写的分频程序,可用得着

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 21 21:27:53 2006 " "Info: Processing started: Sat Oct 21 21:27:53 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FENGPING -c FENGPING " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FENGPING -c FENGPING" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FENGPING.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file FENGPING.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 FENGPING " "Info: Found entity 1: FENGPING" {  } { { "FENGPING.bdf" "" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/FENGPING/FENGPING.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "FENGPING " "Info: Elaborating entity \"FENGPING\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "fenping.vhd 2 1 " "Info: Using design file fenping.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenping-behv " "Info: Found design unit 1: fenping-behv" {  } { { "fenping.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/FENGPING/fenping.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 fenping " "Info: Found entity 1: fenping" {  } { { "fenping.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/FENGPING/fenping.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenping fenping:inst " "Info: Elaborating entity \"fenping\" for hierarchy \"fenping:inst\"" {  } { { "FENGPING.bdf" "inst" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/FENGPING/FENGPING.bdf" { { 80 184 280 176 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SET fenping.vhd(20) " "Warning: VHDL Process Statement warning at fenping.vhd(20): signal \"SET\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fenping.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/FENGPING/fenping.vhd" 20 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "fp.vhd 2 1 " "Info: Using design file fp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fp-a " "Info: Found design unit 1: fp-a" {  } { { "fp.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/FENGPING/fp.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 fp " "Info: Found entity 1: fp" {  } { { "fp.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/FENGPING/fp.vhd" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fp fp:inst1 " "Info: Elaborating entity \"fp\" for hierarchy \"fp:inst1\"" {  } { { "FENGPING.bdf" "inst1" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/FENGPING/FENGPING.bdf" { { 88 400 496 184 "inst1" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SET fp.vhd(23) " "Warning: VHDL Process Statement warning at fp.vhd(23): signal \"SET\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fp.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/FENGPING/fp.vhd" 23 0 0 } }  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "fp.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/FENGPING/fp.vhd" 18 -1 0 } } { "fp.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/FENGPING/fp.vhd" 18 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "31 " "Info: Implemented 31 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "27 " "Info: Implemented 27 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 21 21:27:54 2006 " "Info: Processing ended: Sat Oct 21 21:27:54 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}