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# SOPC Builder class for SRAM Memory
# Written by www.51usb.com
CLASS generic_avalon_sram
{
ASSOCIATED_FILES
{
Add_Program = "default";
Edit_Program = "default";
Generator_Program = "--none--";
}
MODULE_DEFAULTS
{
class = "generic_avalon_sram";
class_version = "2.0";
SLAVE s1
{
PORT_WIRING
{
PORT data
{
width = "8";
is_shared = "1";
direction = "inout";
type = "data";
}
PORT address
{
width = "15";
is_shared = "1";
direction = "input";
type = "address";
}
PORT oe_n
{
width = "1";
is_shared = "1";
direction = "input";
type = "read_n";
}
PORT we_n
{
width = "1";
is_shared = "1";
direction = "input";
type = "write_n";
}
PORT ce_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "chipselect_n";
}
PORT bc_n
{
width = "2";
is_shared = "1";
direction = "input";
#type = "byteenable_n";
type = "milada";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Data_Width = "8";
Address_Width = "15";
Has_IRQ = "0";
IRQ_Number = "N/A";
#Read_Wait_States = "5";
#Write_Wait_States = "4";
Base_Address = "--unknown--";
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "0";
Make_Memory_Model = "0";
}
}
USER_INTERFACE
{
USER_LABELS
{
name = "SRAM Memory";
technology = "Memory";
}
WIZARD_UI default
{
title = "SRAM Memory - {{ $MOD }}";
CONTEXT
{
SBI = "SLAVE s1/SYSTEM_BUILDER_INFO";
SPWA = "SLAVE s1/PORT_WIRING/PORT address";
SPWD = "SLAVE s1/PORT_WIRING/PORT data";
SPWBC = "SLAVE s1/PORT_WIRING/PORT bc_n";
}
align = "center";
IMAGE
{
file="tx.gif";
url="http://www.51usb.com";
}
TEXT
{
layout="flow";
align="centre";
title="SRAM Memory V1.0";
font="bold";
}
GROUP
{
align="centre";
title="Description";
TEXT
{
layout="flow";
align="centre";
title="<P ALIGN=CENTER>
Avalon Tri-State Slave Peripheral<br>
for<br>
Generic SRAM Memory.<br>
</P>";
}
}
GROUP
{
align = "left";
title = "Size";
COMBO address
{
id = "addr";
title = "Address Width: ";
key = "A";
values = "13,14,15,16,17,18,19,20";
suffix = "bits";
DATA
{
$SBI/Address_Width = "$";
$SPWA/width = "$";
}
}
COMBO data
{
values = "8,16";
id = "data";
title = "Data Width: ";
key = "D";
suffix = "bits";
DATA
{
$SBI/Data_Width = "$";
$SPWD/width = "$";
}
$SPWBC/type = "{{
if ($SPWD/width == 16)
{'byteenable_n'}
else
{''}
}}";
}
}
GROUP
{
align = "left";
title = "Timing";
EDIT
{
width = 2;
rows = 1;
columns = 3;
#glue = "0";
suffix = "ns";
type = "int";
title = "Access Time: ";
DATA
{
$$access_time = "$";
}
ACTION initialize
{
$$access_time = "20";
}
}
}
$$ns_per_cycle = "{{ 1E9/$SYS/clock_freq; }}";
$$wait_states = "{{ ceil ($$access_time / $$ns_per_cycle) - 1 }}";
$SBI/Read_Wait_States = "{{ $$wait_states }}";
$SBI/Write_Wait_States = "{{ $$wait_states }}";
$$num_bytes = "{{ 2^($SBI/Address_Width) * $SBI/Data_Width / 8; }}";
$$num_Kbytes = "{{ $$num_bytes / 1024; }}";
$$message_capacity = "SRAM memory capacity: {{ $$num_Kbytes }} Kbytes ({{ $$num_bytes }} bytes)";
message = "{{ $$message_capacity; }}";
$$waitstates_text = "{{ if ($$wait_states == 1) 'waitstate'; else 'waitstates'}}";
$$message_waitstates = "Inserting {{ $SBI/Read_Wait_States }} {{ $$waitstates_text }}";
message = "{{
if ($$wait_states != 0)
{$$message_waitstates}
else
{''}
}}";
}
}
}
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