📄 keyboad.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity keyboad is
port(hang:out std_logic_vector(3 downto 0);
wei:out std_logic_vector(2 downto 0);
ma:out std_logic_vector(3 downto 0);
lie:in std_logic_vector(3 downto 0);
clk:in std_logic);
end keyboad;
architecture jiegou of keyboad is
signal lie_in: std_logic_vector(3 downto 0);
signal clk_a:std_logic:='0';
signal temp_h,temp_l:integer range 3 downto 0 :=0;
begin
wei<="000";
fenpin:process(clk)
variable temp:integer range 19999 downto 0 :=0;
begin
if(clk'event and clk='1')then
if(temp=19999)then
temp:=0;clk_a<=not clk_a;
else
temp:=temp+1;
end if;
end if;
end process fenpin;
g1:process(clk_a)
begin
if(clk_a'event and clk_a='1')then
if(temp_h=3)then
temp_h<=0;
else
temp_h<=temp_h+1;
end if;
case temp_h is
when 0 =>hang<="0001";
when 1 =>hang<="0010";
when 2 =>hang<="0100";
when 3 =>hang<="1000";
when others =>hang<="XXXX";
end case;
end if;
end process g1;
g2:process(lie)
begin
if(lie/="0000")then
lie_in<=lie;
case lie_in is
when "0001" =>temp_l<=0;
when "0010" =>temp_l<=1;
when "0100" =>temp_l<=2;
when "1000" =>temp_l<=3;
when others=>temp_l<=0;
end case;
if(temp_h=0)then
if(temp_l=0)then
ma<="0000";
elsif(temp_l=1)then
ma<="0001";
elsif(temp_l=2)then
ma<="0010";
else
ma<="0011";
end if;
elsif(temp_h=1)then
if(temp_l=0)then
ma<="0100";
elsif(temp_l=1)then
ma<="0101";
elsif(temp_l=2)then
ma<="0110";
else
ma<="0111";
end if;
elsif(temp_h=2)then
if(temp_l=0)then
ma<="1000";
elsif(temp_l=1)then
ma<="1001";
elsif(temp_l=2)then
ma<="1010";
else
ma<="1011";
end if;
elsif(temp_h=3)then
if(temp_l=0)then
ma<="1100";
elsif(temp_l=1)then
ma<="1101";
elsif(temp_l=2)then
ma<="1110";
else
ma<="1111";
end if;
end if;
end if;
end process g2;
end jiegou;
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