pinlv.tan.qmsg

基于单片机与CPLD的 等精度频率计

{ "Info" "ITDB_TH_RESULT" "ena gate fxclk -3.000 ns register " "Info: th for register \"ena\" (data pin = \"gate\", clock pin = \"fxclk\") is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fxclk destination 3.000 ns + Longest register " "Info: + Longest clock path from clock \"fxclk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns fxclk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'fxclk'" {  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fxclk } "NODE_NAME" } } { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns ena 2 REG LC49 65 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC49; Fanout = 65; REG Node = 'ena'" {  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { fxclk ena } "NODE_NAME" } } { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { fxclk ena } "NODE_NAME" } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { fxclk fxclk~out ena } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns gate 1 PIN PIN_34 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_34; Fanout = 1; PIN Node = 'gate'" {  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gate } "NODE_NAME" } } { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns ena 2 REG LC49 65 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC49; Fanout = 65; REG Node = 'ena'" {  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { gate ena } "NODE_NAME" } } { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { gate ena } "NODE_NAME" } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { gate gate~out ena } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { fxclk ena } "NODE_NAME" } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { fxclk fxclk~out ena } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { gate ena } "NODE_NAME" } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { gate gate~out ena } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 30 21:30:31 2006 " "Info: Processing ended: Thu Nov 30 21:30:31 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}