pinlv.tan.qmsg

基于单片机与CPLD的 等精度频率计

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "fsclk " "Info: Assuming node \"fsclk\" is an undefined clock" {  } { { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 7 -1 0 } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fsclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "fxclk " "Info: Assuming node \"fxclk\" is an undefined clock" {  } { { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 6 -1 0 } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fxclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "fsclk register \\miao_1:temp\[0\] register \\miao_1:temp\[8\] 71.43 MHz 14.0 ns Internal " "Info: Clock \"fsclk\" has Internal fmax of 71.43 MHz between source register \"\\miao_1:temp\[0\]\" and destination register \"\\miao_1:temp\[8\]\" (period= 14.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register register " "Info: + Longest register to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\miao_1:temp\[0\] 1 REG LC121 34 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC121; Fanout = 34; REG Node = '\\miao_1:temp\[0\]'" {  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { \miao_1:temp[0] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns temp~132 2 COMB LC33 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC33; Fanout = 1; COMB Node = 'temp~132'" {  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { \miao_1:temp[0] temp~132 } "NODE_NAME" } } { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns \\miao_1:temp\[8\] 3 REG LC34 34 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC34; Fanout = 34; REG Node = '\\miao_1:temp\[8\]'" {  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { temp~132 \miao_1:temp[8] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns ( 77.78 % ) " "Info: Total cell delay = 7.000 ns ( 77.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 22.22 % ) " "Info: Total interconnect delay = 2.000 ns ( 22.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.000 ns" { \miao_1:temp[0] temp~132 \miao_1:temp[8] } "NODE_NAME" } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "9.000 ns" { \miao_1:temp[0] temp~132 \miao_1:temp[8] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fsclk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"fsclk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns fsclk 1 CLK PIN_2 58 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_2; Fanout = 58; CLK Node = 'fsclk'" {  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fsclk } "NODE_NAME" } } { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns \\miao_1:temp\[8\] 2 REG LC34 34 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC34; Fanout = 34; REG Node = '\\miao_1:temp\[8\]'" {  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { fsclk \miao_1:temp[8] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { fsclk \miao_1:temp[8] } "NODE_NAME" } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { fsclk fsclk~out \miao_1:temp[8] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fsclk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"fsclk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns fsclk 1 CLK PIN_2 58 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_2; Fanout = 58; CLK Node = 'fsclk'" {  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fsclk } "NODE_NAME" } } { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns \\miao_1:temp\[0\] 2 REG LC121 34 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC121; Fanout = 34; REG Node = '\\miao_1:temp\[0\]'" {  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { fsclk \miao_1:temp[0] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { fsclk \miao_1:temp[0] } "NODE_NAME" } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { fsclk fsclk~out \miao_1:temp[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { fsclk \miao_1:temp[8] } "NODE_NAME" } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { fsclk fsclk~out \miao_1:temp[8] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { fsclk \miao_1:temp[0] } "NODE_NAME" } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { fsclk fsclk~out \miao_1:temp[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.000 ns" { \miao_1:temp[0] temp~132 \miao_1:temp[8] } "NODE_NAME" } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "9.000 ns" { \miao_1:temp[0] temp~132 \miao_1:temp[8] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns } } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { fsclk \miao_1:temp[8] } "NODE_NAME" } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { fsclk fsclk~out \miao_1:temp[8] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { fsclk \miao_1:temp[0] } "NODE_NAME" } } { "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { fsclk fsclk~out \miao_1:temp[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}