pinlv.map.qmsg

基于单片机与CPLD的 等精度频率计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 30 21:30:14 2006 " "Info: Processing started: Thu Nov 30 21:30:14 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pinlv -c pinlv " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pinlv -c pinlv" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pinlv.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pinlv.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pinlv-jiegou " "Info: Found design unit 1: pinlv-jiegou" {  } { { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pinlv " "Info: Found entity 1: pinlv" {  } { { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "pinlv " "Info: Elaborating entity \"pinlv\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "nx\[0\]~32 32 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: \"nx\[0\]~32\"" {  } { { "pinlv.vhd" "nx\[0\]~32" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 33 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "ns\[0\]~32 32 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: \"ns\[0\]~32\"" {  } { { "pinlv.vhd" "ns\[0\]~32" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 44 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:nx_rtl_0 " "Info: Elaborated megafunction instantiation \"lpm_counter:nx_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add2\"" {  } { { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 69 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|addcore:adder\[3\] lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add2\|addcore:adder\[3\]\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 276 9 0 } } { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 69 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add2 " "Info: Instantiated megafunction \"lpm_add_sub:Add2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 25 " "Info: Parameter \"LPM_WIDTH\" = \"25\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 69 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|addcore:adder\[3\]\|a_csnbuffer:oflow_node lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add2\|addcore:adder\[3\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" {  } { { "addcore.tdf" "" { Text "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 69 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add2 " "Info: Instantiated megafunction \"lpm_add_sub:Add2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 25 " "Info: Parameter \"LPM_WIDTH\" = \"25\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 69 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|addcore:adder\[3\]\|a_csnbuffer:result_node lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add2\|addcore:adder\[3\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" {  } { { "addcore.tdf" "" { Text "d:/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/libraries/megafunctions/addcore.tdf" 186 5 0 } } { "pinlv.vhd" "" { Text "F:/chengxu/VHDL/QU/pinlv/pinlv.vhd" 69 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}