ps2tolcd.fit.qmsg

1、ps/2键盘输入

{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "4 unused 3.30 0 4 0 " "Info: Number of I/O pins in group: 4 (unused VREF, 3.30 VCCIO, 0 input, 4 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 18 26 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 18 total pin(s) used --  26 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.30V 1 47 " "Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 1 total pin(s) used --  47 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 2 43 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  43 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 48 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.103 ns register register " "Info: Estimated most critical path is register to register delay of 2.103 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ps2_keyboard_interface:inst3\|rx_released 1 REG LAB_X8_Y11 37 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X8_Y11; Fanout = 37; REG Node = 'ps2_keyboard_interface:inst3\|rx_released'" {  } { { "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/code/EP1C6/S7_PS2_LCD/PROJ/" "" "" { ps2_keyboard_interface:inst3|rx_released } "NODE_NAME" } "" } } { "../SRC/ps2_keyboard.v" "" { Text "E:/code/EP1C6/S7_PS2_LCD/SRC/ps2_keyboard.v" 188 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.794 ns) + CELL(0.309 ns) 2.103 ns lcd:inst2\|lcd_e 2 REG LAB_X7_Y17 2 " "Info: 2: + IC(1.794 ns) + CELL(0.309 ns) = 2.103 ns; Loc. = LAB_X7_Y17; Fanout = 2; REG Node = 'lcd:inst2\|lcd_e'" {  } { { "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/code/EP1C6/S7_PS2_LCD/PROJ/" "" "2.103 ns" { ps2_keyboard_interface:inst3|rx_released lcd:inst2|lcd_e } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/code/EP1C6/S7_PS2_LCD/SRC/lcd.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 14.69 % " "Info: Total cell delay = 0.309 ns ( 14.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.794 ns 85.31 % " "Info: Total interconnect delay = 1.794 ns ( 85.31 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/code/EP1C6/S7_PS2_LCD/PROJ/" "" "2.103 ns" { ps2_keyboard_interface:inst3|rx_released lcd:inst2|lcd_e } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 4 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 4%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "1 " "Warning: The following 1 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ps2_clk a permanently enabled " "Info: Pin ps2_clk has a permanently enabled output enable" {  } { { "ps2tolcd.bdf" "" { Schematic "E:/code/EP1C6/S7_PS2_LCD/PROJ/ps2tolcd.bdf" { { 264 608 784 280 "ps2_clk" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ps2_clk" } } } } { "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/code/EP1C6/S7_PS2_LCD/PROJ/" "" "" { ps2_clk } "NODE_NAME" } "" } } { "E:/code/EP1C6/S7_PS2_LCD/PROJ/ps2tolcd.fld" "" { Floorplan "E:/code/EP1C6/S7_PS2_LCD/PROJ/ps2tolcd.fld" "" "" { ps2_clk } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: The following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "lcd_rw GND " "Info: Pin lcd_rw has GND driving its datain port" {  } { { "ps2tolcd.bdf" "" { Schematic "E:/code/EP1C6/S7_PS2_LCD/PROJ/ps2tolcd.bdf" { { 560 856 1032 576 "lcd_rw" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd_rw" } } } } { "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/code/EP1C6/S7_PS2_LCD/PROJ/" "" "" { lcd_rw } "NODE_NAME" } "" } } { "E:/code/EP1C6/S7_PS2_LCD/PROJ/ps2tolcd.fld" "" { Floorplan "E:/code/EP1C6/S7_PS2_LCD/PROJ/ps2tolcd.fld" "" "" { lcd_rw } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "led\[7\] GND " "Info: Pin led\[7\] has GND driving its datain port" {  } { { "ps2tolcd.bdf" "" { Schematic "E:/code/EP1C6/S7_PS2_LCD/PROJ/ps2tolcd.bdf" { { 360 624 800 376 "led\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led\[7\]" } } } } { "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/code/EP1C6/S7_PS2_LCD/PROJ/" "" "" { led[7] } "NODE_NAME" } "" } } { "E:/code/EP1C6/S7_PS2_LCD/PROJ/ps2tolcd.fld" "" { Floorplan "E:/code/EP1C6/S7_PS2_LCD/PROJ/ps2tolcd.fld" "" "" { led[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ps2_clk VCC " "Info: Pin ps2_clk has VCC driving its datain port" {  } { { "ps2tolcd.bdf" "" { Schematic "E:/code/EP1C6/S7_PS2_LCD/PROJ/ps2tolcd.bdf" { { 264 608 784 280 "ps2_clk" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ps2_clk" } } } } { "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/code/EP1C6/S7_PS2_LCD/PROJ/" "" "" { ps2_clk } "NODE_NAME" } "" } } { "E:/code/EP1C6/S7_PS2_LCD/PROJ/ps2tolcd.fld" "" { Floorplan "E:/code/EP1C6/S7_PS2_LCD/PROJ/ps2tolcd.fld" "" "" { ps2_clk } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: The following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "ps2_keyboard_interface:inst3\|ps2_data_hi_z~29 " "Info: The following pins have the same output enable: ps2_keyboard_interface:inst3\|ps2_data_hi_z~29" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ps2_data LVTTL " "Info: Type bidirectional pin ps2_data uses the LVTTL I/O standard" {  } { { "ps2tolcd.bdf" "" { Schematic "E:/code/EP1C6/S7_PS2_LCD/PROJ/ps2tolcd.bdf" { { 280 608 784 296 "ps2_data" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ps2_data" } } } } { "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/code/EP1C6/S7_PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/code/EP1C6/S7_PS2_LCD/PROJ/" "" "" { ps2_data } "NODE_NAME" } "" } } { "E:/code/EP1C6/S7_PS2_LCD/PROJ/ps2tolcd.fld" "" { Floorplan "E:/code/EP1C6/S7_PS2_LCD/PROJ/ps2tolcd.fld" "" "" { ps2_data } "NODE_NAME" } }  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 23 10:16:59 2006 " "Info: Processing ended: Thu Feb 23 10:16:59 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}