standalone.ucf

基于FPGA与LM4550B的AC97软声卡VHDL语言驱动

Net ClkIn LOC=AJ15;
Net ClkIn IOSTANDARD = LVCMOS25;
Net ClkIn PERIOD = 10000 ps;

Net Reset_n LOC=AH5;
Net Reset_n IOSTANDARD = LVTTL;
Net Reset_n TIG;

NET AC97Clk PERIOD = 10000 ps;
NET "AC97Clk" TNM_NET = "ac97bitclk_grp";

### AC97 Signals ###
NET AC97Clk   LOC = F8;
NET AC97RESET_N   LOC = E6;
NET SYNC     LOC = F7;
NET SDATA_OUT LOC = E8;
NET SDATA_IN  LOC = E9;

NET AC97Clk   IOSTANDARD = LVTTL;
NET AC97RESET_N   IOSTANDARD = LVTTL;
NET SYNC     IOSTANDARD = LVTTL;
NET SDATA_OUT IOSTANDARD = LVTTL;
NET SDATA_IN  IOSTANDARD = LVTTL;

NET AC97RESET_N   DRIVE = 8 | SLEW = SLOW;
NET SYNC     DRIVE = 8 | SLEW = SLOW;
NET SDATA_OUT DRIVE = 8 | SLEW = SLOW;

Net LED<0> LOC=AC4;
Net LED<0> IOSTANDARD = LVTTL;
Net LED<0> SLEW = SLOW;
Net LED<0> DRIVE = 12;
Net LED<1> LOC=AC3;
Net LED<1> IOSTANDARD = LVTTL;
Net LED<1> SLEW = SLOW;
Net LED<1> DRIVE = 12;
Net LED<2> LOC=AA6;
Net LED<2> IOSTANDARD = LVTTL;
Net LED<2> SLEW = SLOW;
Net LED<2> DRIVE = 12;
Net LED<3> LOC=AA5;
Net LED<3> IOSTANDARD = LVTTL;
Net LED<3> SLEW = SLOW;
Net LED<3> DRIVE = 12;

NET DEBUG<0>   LOC = N5; # J5.5
NET DEBUG<1>   LOC = L4; # J5.7
NET DEBUG<2>   LOC = N2; # J5.9
NET DEBUG<3>   LOC = R9; # J5.11
NET DEBUG<4>   LOC = M3; # J5.13
NET DEBUG*  IOSTANDARD = LVTTL;