decoder.v
来自「这里有verilog编写的8051ipcore 谁要啊?」· Verilog 代码 · 共 2,242 行 · 第 1/5 页
V
2,242 行
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`MOV_R : begin
ram_rd_sel = `RRS_RN;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`MOV_AR : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_RN;
src_sel1 = `ASS_ACC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`MOV_DR : begin
ram_rd_sel = `RRS_D;
ram_wr_sel = `RWS_RN;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`MOV_CR : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_RN;
src_sel1 = `ASS_IMM;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP2;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`MOV_RD : begin
ram_rd_sel = `RRS_RN;
ram_wr_sel = `RWS_D;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`ORL_R : begin
ram_rd_sel = `RRS_RN;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_ACC;
alu_op = `ALU_OR;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`SUBB_R : begin
ram_rd_sel = `RRS_RN;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_ACC;
alu_op = `ALU_SUB;
wr = 1'b1;
psw_set = `PS_AC;
cy_sel = `CY_PSW;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`XCH_R : begin
ram_rd_sel = `RRS_RN;
ram_wr_sel = `RWS_RN;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_ACC;
alu_op = `ALU_XCH;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_1;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_Y;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`XRL_R : begin
ram_rd_sel = `RRS_RN;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_ACC;
alu_op = `ALU_XOR;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
//op_code [7:1]
`ADD_I : begin
ram_rd_sel = `RRS_I;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_ACC;
src_sel2 = `ASS_RAM;
alu_op = `ALU_ADD;
wr = 1'b1;
psw_set = `PS_AC;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`ADDC_I : begin
ram_rd_sel = `RRS_I;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_ACC;
src_sel2 = `ASS_RAM;
alu_op = `ALU_ADD;
wr = 1'b1;
psw_set = `PS_AC;
cy_sel = `CY_PSW;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`ANL_I : begin
ram_rd_sel = `RRS_I;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_ACC;
src_sel2 = `ASS_RAM;
alu_op = `ALU_AND;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`CJNE_I : begin
ram_rd_sel = `RRS_I;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_IMM;
src_sel2 = `ASS_RAM;
alu_op = `ALU_SUB;
wr = 1'b0;
psw_set = `PS_CY;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP2;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`DEC_I : begin
ram_rd_sel = `RRS_I;
ram_wr_sel = `RWS_I;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_ZERO;
alu_op = `ALU_SUB;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_1;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`INC_I : begin
ram_rd_sel = `RRS_I;
ram_wr_sel = `RWS_I;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_ZERO;
alu_op = `ALU_ADD;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_1;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`MOV_I : begin
ram_rd_sel = `RRS_I;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`MOV_ID : begin
ram_rd_sel = `RRS_I;
ram_wr_sel = `RWS_D;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`MOV_AI : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_I;
src_sel1 = `ASS_ACC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`MOV_DI : begin
ram_rd_sel = `RRS_D;
ram_wr_sel = `RWS_I;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`MOV_CI : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_I;
src_sel1 = `ASS_IMM;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP2;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`MOVX_IA : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_XRAM;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP2;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_RI;
end
`MOVX_AI :begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_OP2;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_RI;
end
`ORL_I : begin
ram_rd_sel = `RRS_I;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_ACC;
alu_op = `ALU_OR;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`SUBB_I : begin
ram_rd_sel = `RRS_I;
ram_wr_sel = `RWS_ACC;
src_sel1 = `ASS_RAM;
src_sel2 = `ASS_ACC;
alu_op = `ALU_SUB;
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