overflow_test.v

来自「基于FPGA的技术溢出研究程序」· Verilog 代码 · 共 18 行

module overflow_test(clk,ena,Fword,address);
  input clk;
  input ena;
  input [13:0]Fword;
  output [9:0]address;
  reg [9:0]address;
  reg [21:0]outdata;
  always@(posedge clk)
    begin
      if(!ena)
        begin
          outdata<=outdata+Fword;
          address<=outdata[21:12];
        end
      else
      outdata<=0;
    end
endmodule