overflow_test.fit.qmsg

基于FPGA的技术溢出研究程序

{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 16 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  16 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 23 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  23 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 1 22 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  22 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 24 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.712 ns register register " "Info: Estimated most critical path is register to register delay of 3.712 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns outdata\[0\] 1 REG LAB_X27_Y6 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X27_Y6; Fanout = 2; REG Node = 'outdata\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { outdata[0] } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.596 ns) 1.271 ns outdata\[0\]~200 2 COMB LAB_X27_Y6 2 " "Info: 2: + IC(0.675 ns) + CELL(0.596 ns) = 1.271 ns; Loc. = LAB_X27_Y6; Fanout = 2; COMB Node = 'outdata\[0\]~200'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.271 ns" { outdata[0] outdata[0]~200 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.357 ns outdata\[1\]~201 3 COMB LAB_X27_Y6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.357 ns; Loc. = LAB_X27_Y6; Fanout = 2; COMB Node = 'outdata\[1\]~201'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[0]~200 outdata[1]~201 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.443 ns outdata\[2\]~202 4 COMB LAB_X27_Y6 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.443 ns; Loc. = LAB_X27_Y6; Fanout = 2; COMB Node = 'outdata\[2\]~202'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[1]~201 outdata[2]~202 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.529 ns outdata\[3\]~203 5 COMB LAB_X27_Y6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.529 ns; Loc. = LAB_X27_Y6; Fanout = 2; COMB Node = 'outdata\[3\]~203'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[2]~202 outdata[3]~203 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.615 ns outdata\[4\]~204 6 COMB LAB_X27_Y6 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.615 ns; Loc. = LAB_X27_Y6; Fanout = 2; COMB Node = 'outdata\[4\]~204'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[3]~203 outdata[4]~204 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.701 ns outdata\[5\]~205 7 COMB LAB_X27_Y6 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.701 ns; Loc. = LAB_X27_Y6; Fanout = 2; COMB Node = 'outdata\[5\]~205'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[4]~204 outdata[5]~205 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.787 ns outdata\[6\]~206 8 COMB LAB_X27_Y6 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.787 ns; Loc. = LAB_X27_Y6; Fanout = 2; COMB Node = 'outdata\[6\]~206'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[5]~205 outdata[6]~206 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.873 ns outdata\[7\]~207 9 COMB LAB_X27_Y6 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 1.873 ns; Loc. = LAB_X27_Y6; Fanout = 2; COMB Node = 'outdata\[7\]~207'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[6]~206 outdata[7]~207 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.959 ns outdata\[8\]~208 10 COMB LAB_X27_Y6 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 1.959 ns; Loc. = LAB_X27_Y6; Fanout = 2; COMB Node = 'outdata\[8\]~208'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[7]~207 outdata[8]~208 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.045 ns outdata\[9\]~209 11 COMB LAB_X27_Y6 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.045 ns; Loc. = LAB_X27_Y6; Fanout = 2; COMB Node = 'outdata\[9\]~209'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[8]~208 outdata[9]~209 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.131 ns outdata\[10\]~210 12 COMB LAB_X27_Y6 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.131 ns; Loc. = LAB_X27_Y6; Fanout = 2; COMB Node = 'outdata\[10\]~210'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[9]~209 outdata[10]~210 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.107 ns) + CELL(0.086 ns) 2.324 ns outdata\[11\]~211 13 COMB LAB_X27_Y5 2 " "Info: 13: + IC(0.107 ns) + CELL(0.086 ns) = 2.324 ns; Loc. = LAB_X27_Y5; Fanout = 2; COMB Node = 'outdata\[11\]~211'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.193 ns" { outdata[10]~210 outdata[11]~211 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.410 ns outdata\[12\]~212 14 COMB LAB_X27_Y5 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.410 ns; Loc. = LAB_X27_Y5; Fanout = 2; COMB Node = 'outdata\[12\]~212'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[11]~211 outdata[12]~212 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.496 ns outdata\[13\]~213 15 COMB LAB_X27_Y5 2 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.496 ns; Loc. = LAB_X27_Y5; Fanout = 2; COMB Node = 'outdata\[13\]~213'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[12]~212 outdata[13]~213 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.582 ns outdata\[14\]~214 16 COMB LAB_X27_Y5 2 " "Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 2.582 ns; Loc. = LAB_X27_Y5; Fanout = 2; COMB Node = 'outdata\[14\]~214'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[13]~213 outdata[14]~214 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.668 ns outdata\[15\]~215 17 COMB LAB_X27_Y5 2 " "Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 2.668 ns; Loc. = LAB_X27_Y5; Fanout = 2; COMB Node = 'outdata\[15\]~215'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[14]~214 outdata[15]~215 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.754 ns outdata\[16\]~216 18 COMB LAB_X27_Y5 2 " "Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 2.754 ns; Loc. = LAB_X27_Y5; Fanout = 2; COMB Node = 'outdata\[16\]~216'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[15]~215 outdata[16]~216 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.840 ns outdata\[17\]~217 19 COMB LAB_X27_Y5 2 " "Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 2.840 ns; Loc. = LAB_X27_Y5; Fanout = 2; COMB Node = 'outdata\[17\]~217'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[16]~216 outdata[17]~217 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.926 ns outdata\[18\]~218 20 COMB LAB_X27_Y5 2 " "Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 2.926 ns; Loc. = LAB_X27_Y5; Fanout = 2; COMB Node = 'outdata\[18\]~218'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[17]~217 outdata[18]~218 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.012 ns outdata\[19\]~219 21 COMB LAB_X27_Y5 2 " "Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 3.012 ns; Loc. = LAB_X27_Y5; Fanout = 2; COMB Node = 'outdata\[19\]~219'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[18]~218 outdata[19]~219 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.098 ns outdata\[20\]~220 22 COMB LAB_X27_Y5 1 " "Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 3.098 ns; Loc. = LAB_X27_Y5; Fanout = 1; COMB Node = 'outdata\[20\]~220'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[19]~219 outdata[20]~220 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 3.604 ns outdata\[21\]~187 23 COMB LAB_X27_Y5 1 " "Info: 23: + IC(0.000 ns) + CELL(0.506 ns) = 3.604 ns; Loc. = LAB_X27_Y5; Fanout = 1; COMB Node = 'outdata\[21\]~187'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.506 ns" { outdata[20]~220 outdata[21]~187 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.712 ns outdata\[21\] 24 REG LAB_X27_Y5 2 " "Info: 24: + IC(0.000 ns) + CELL(0.108 ns) = 3.712 ns; Loc. = LAB_X27_Y5; Fanout = 2; REG Node = 'outdata\[21\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { outdata[21]~187 outdata[21] } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.930 ns ( 78.93 % ) " "Info: Total cell delay = 2.930 ns ( 78.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 21.07 % ) " "Info: Total interconnect delay = 0.782 ns ( 21.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.712 ns" { outdata[0] outdata[0]~200 outdata[1]~201 outdata[2]~202 outdata[3]~203 outdata[4]~204 outdata[5]~205 outdata[6]~206 outdata[7]~207 outdata[8]~208 outdata[9]~209 outdata[10]~210 outdata[11]~211 outdata[12]~212 outdata[13]~213 outdata[14]~214 outdata[15]~215 outdata[16]~216 outdata[17]~217 outdata[18]~218 outdata[19]~219 outdata[20]~220 outdata[21]~187 outdata[21] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x14_y0 x28_y14 " "Info: The peak interconnect region extends from location x14_y0 to location x28_y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}