overflow_test.tan.qmsg

基于FPGA的技术溢出研究程序

{ "Info" "ITDB_FULL_TCO_RESULT" "clk address\[7\] address\[7\]~reg0 8.499 ns register " "Info: tco from clock \"clk\" to destination pin \"address\[7\]\" through register \"address\[7\]~reg0\" is 8.499 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.748 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.748 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 2.748 ns address\[7\]~reg0 3 REG LCFF_X27_Y5_N25 1 " "Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.748 ns; Loc. = LCFF_X27_Y5_N25; Fanout = 1; REG Node = 'address\[7\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.505 ns" { clk~clkctrl address[7]~reg0 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 64.26 % ) " "Info: Total cell delay = 1.766 ns ( 64.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.982 ns ( 35.74 % ) " "Info: Total interconnect delay = 0.982 ns ( 35.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.748 ns" { clk clk~clkctrl address[7]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.748 ns" { clk clk~combout clk~clkctrl address[7]~reg0 } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.447 ns + Longest register pin " "Info: + Longest register to pin delay is 5.447 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns address\[7\]~reg0 1 REG LCFF_X27_Y5_N25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y5_N25; Fanout = 1; REG Node = 'address\[7\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { address[7]~reg0 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.211 ns) + CELL(3.236 ns) 5.447 ns address\[7\] 2 PIN PIN_119 0 " "Info: 2: + IC(2.211 ns) + CELL(3.236 ns) = 5.447 ns; Loc. = PIN_119; Fanout = 0; PIN Node = 'address\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.447 ns" { address[7]~reg0 address[7] } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns ( 59.41 % ) " "Info: Total cell delay = 3.236 ns ( 59.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.211 ns ( 40.59 % ) " "Info: Total interconnect delay = 2.211 ns ( 40.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.447 ns" { address[7]~reg0 address[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.447 ns" { address[7]~reg0 address[7] } { 0.000ns 2.211ns } { 0.000ns 3.236ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.748 ns" { clk clk~clkctrl address[7]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.748 ns" { clk clk~combout clk~clkctrl address[7]~reg0 } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.447 ns" { address[7]~reg0 address[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.447 ns" { address[7]~reg0 address[7] } { 0.000ns 2.211ns } { 0.000ns 3.236ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "outdata\[3\] Fword\[3\] clk 0.221 ns register " "Info: th for register \"outdata\[3\]\" (data pin = \"Fword\[3\]\", clock pin = \"clk\") is 0.221 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.736 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.827 ns) + CELL(0.666 ns) 2.736 ns outdata\[3\] 3 REG LCFF_X27_Y6_N17 2 " "Info: 3: + IC(0.827 ns) + CELL(0.666 ns) = 2.736 ns; Loc. = LCFF_X27_Y6_N17; Fanout = 2; REG Node = 'outdata\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { clk~clkctrl outdata[3] } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 64.55 % ) " "Info: Total cell delay = 1.766 ns ( 64.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.970 ns ( 35.45 % ) " "Info: Total interconnect delay = 0.970 ns ( 35.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.736 ns" { clk clk~clkctrl outdata[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.736 ns" { clk clk~combout clk~clkctrl outdata[3] } { 0.000ns 0.000ns 0.143ns 0.827ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.821 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.821 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns Fword\[3\] 1 PIN PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_91; Fanout = 2; PIN Node = 'Fword\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Fword[3] } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.615 ns) 2.713 ns outdata\[3\]~196 2 COMB LCCOMB_X27_Y6_N16 1 " "Info: 2: + IC(0.988 ns) + CELL(0.615 ns) = 2.713 ns; Loc. = LCCOMB_X27_Y6_N16; Fanout = 1; COMB Node = 'outdata\[3\]~196'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.603 ns" { Fword[3] outdata[3]~196 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.821 ns outdata\[3\] 3 REG LCFF_X27_Y6_N17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.821 ns; Loc. = LCFF_X27_Y6_N17; Fanout = 2; REG Node = 'outdata\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { outdata[3]~196 outdata[3] } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.833 ns ( 64.98 % ) " "Info: Total cell delay = 1.833 ns ( 64.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.988 ns ( 35.02 % ) " "Info: Total interconnect delay = 0.988 ns ( 35.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.821 ns" { Fword[3] outdata[3]~196 outdata[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.821 ns" { Fword[3] Fword[3]~combout outdata[3]~196 outdata[3] } { 0.000ns 0.000ns 0.988ns 0.000ns } { 0.000ns 1.110ns 0.615ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.736 ns" { clk clk~clkctrl outdata[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.736 ns" { clk clk~combout clk~clkctrl outdata[3] } { 0.000ns 0.000ns 0.143ns 0.827ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.821 ns" { Fword[3] outdata[3]~196 outdata[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.821 ns" { Fword[3] Fword[3]~combout outdata[3]~196 outdata[3] } { 0.000ns 0.000ns 0.988ns 0.000ns } { 0.000ns 1.110ns 0.615ns 0.108ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}