overflow_test.tan.qmsg

基于FPGA的技术溢出研究程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register outdata\[0\] register outdata\[21\] 252.27 MHz 3.964 ns Internal " "Info: Clock \"clk\" has Internal fmax of 252.27 MHz between source register \"outdata\[0\]\" and destination register \"outdata\[21\]\" (period= 3.964 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.712 ns + Longest register register " "Info: + Longest register to register delay is 3.712 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns outdata\[0\] 1 REG LCFF_X27_Y6_N11 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y6_N11; Fanout = 2; REG Node = 'outdata\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { outdata[0] } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.460 ns) + CELL(0.621 ns) 1.081 ns outdata\[0\]~200 2 COMB LCCOMB_X27_Y6_N10 2 " "Info: 2: + IC(0.460 ns) + CELL(0.621 ns) = 1.081 ns; Loc. = LCCOMB_X27_Y6_N10; Fanout = 2; COMB Node = 'outdata\[0\]~200'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.081 ns" { outdata[0] outdata[0]~200 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.167 ns outdata\[1\]~201 3 COMB LCCOMB_X27_Y6_N12 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.167 ns; Loc. = LCCOMB_X27_Y6_N12; Fanout = 2; COMB Node = 'outdata\[1\]~201'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[0]~200 outdata[1]~201 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 1.357 ns outdata\[2\]~202 4 COMB LCCOMB_X27_Y6_N14 2 " "Info: 4: + IC(0.000 ns) + CELL(0.190 ns) = 1.357 ns; Loc. = LCCOMB_X27_Y6_N14; Fanout = 2; COMB Node = 'outdata\[2\]~202'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.190 ns" { outdata[1]~201 outdata[2]~202 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.443 ns outdata\[3\]~203 5 COMB LCCOMB_X27_Y6_N16 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.443 ns; Loc. = LCCOMB_X27_Y6_N16; Fanout = 2; COMB Node = 'outdata\[3\]~203'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[2]~202 outdata[3]~203 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.529 ns outdata\[4\]~204 6 COMB LCCOMB_X27_Y6_N18 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.529 ns; Loc. = LCCOMB_X27_Y6_N18; Fanout = 2; COMB Node = 'outdata\[4\]~204'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[3]~203 outdata[4]~204 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.615 ns outdata\[5\]~205 7 COMB LCCOMB_X27_Y6_N20 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.615 ns; Loc. = LCCOMB_X27_Y6_N20; Fanout = 2; COMB Node = 'outdata\[5\]~205'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[4]~204 outdata[5]~205 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.701 ns outdata\[6\]~206 8 COMB LCCOMB_X27_Y6_N22 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.701 ns; Loc. = LCCOMB_X27_Y6_N22; Fanout = 2; COMB Node = 'outdata\[6\]~206'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[5]~205 outdata[6]~206 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.787 ns outdata\[7\]~207 9 COMB LCCOMB_X27_Y6_N24 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 1.787 ns; Loc. = LCCOMB_X27_Y6_N24; Fanout = 2; COMB Node = 'outdata\[7\]~207'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[6]~206 outdata[7]~207 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.873 ns outdata\[8\]~208 10 COMB LCCOMB_X27_Y6_N26 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 1.873 ns; Loc. = LCCOMB_X27_Y6_N26; Fanout = 2; COMB Node = 'outdata\[8\]~208'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[7]~207 outdata[8]~208 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.959 ns outdata\[9\]~209 11 COMB LCCOMB_X27_Y6_N28 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 1.959 ns; Loc. = LCCOMB_X27_Y6_N28; Fanout = 2; COMB Node = 'outdata\[9\]~209'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[8]~208 outdata[9]~209 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.175 ns) 2.134 ns outdata\[10\]~210 12 COMB LCCOMB_X27_Y6_N30 2 " "Info: 12: + IC(0.000 ns) + CELL(0.175 ns) = 2.134 ns; Loc. = LCCOMB_X27_Y6_N30; Fanout = 2; COMB Node = 'outdata\[10\]~210'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.175 ns" { outdata[9]~209 outdata[10]~210 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.220 ns outdata\[11\]~211 13 COMB LCCOMB_X27_Y5_N0 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.220 ns; Loc. = LCCOMB_X27_Y5_N0; Fanout = 2; COMB Node = 'outdata\[11\]~211'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[10]~210 outdata[11]~211 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.306 ns outdata\[12\]~212 14 COMB LCCOMB_X27_Y5_N2 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.306 ns; Loc. = LCCOMB_X27_Y5_N2; Fanout = 2; COMB Node = 'outdata\[12\]~212'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[11]~211 outdata[12]~212 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.392 ns outdata\[13\]~213 15 COMB LCCOMB_X27_Y5_N4 2 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.392 ns; Loc. = LCCOMB_X27_Y5_N4; Fanout = 2; COMB Node = 'outdata\[13\]~213'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[12]~212 outdata[13]~213 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.478 ns outdata\[14\]~214 16 COMB LCCOMB_X27_Y5_N6 2 " "Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 2.478 ns; Loc. = LCCOMB_X27_Y5_N6; Fanout = 2; COMB Node = 'outdata\[14\]~214'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[13]~213 outdata[14]~214 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.564 ns outdata\[15\]~215 17 COMB LCCOMB_X27_Y5_N8 2 " "Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 2.564 ns; Loc. = LCCOMB_X27_Y5_N8; Fanout = 2; COMB Node = 'outdata\[15\]~215'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[14]~214 outdata[15]~215 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.650 ns outdata\[16\]~216 18 COMB LCCOMB_X27_Y5_N10 2 " "Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 2.650 ns; Loc. = LCCOMB_X27_Y5_N10; Fanout = 2; COMB Node = 'outdata\[16\]~216'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[15]~215 outdata[16]~216 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.736 ns outdata\[17\]~217 19 COMB LCCOMB_X27_Y5_N12 2 " "Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 2.736 ns; Loc. = LCCOMB_X27_Y5_N12; Fanout = 2; COMB Node = 'outdata\[17\]~217'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[16]~216 outdata[17]~217 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 2.926 ns outdata\[18\]~218 20 COMB LCCOMB_X27_Y5_N14 2 " "Info: 20: + IC(0.000 ns) + CELL(0.190 ns) = 2.926 ns; Loc. = LCCOMB_X27_Y5_N14; Fanout = 2; COMB Node = 'outdata\[18\]~218'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.190 ns" { outdata[17]~217 outdata[18]~218 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.012 ns outdata\[19\]~219 21 COMB LCCOMB_X27_Y5_N16 2 " "Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 3.012 ns; Loc. = LCCOMB_X27_Y5_N16; Fanout = 2; COMB Node = 'outdata\[19\]~219'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[18]~218 outdata[19]~219 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.098 ns outdata\[20\]~220 22 COMB LCCOMB_X27_Y5_N18 1 " "Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 3.098 ns; Loc. = LCCOMB_X27_Y5_N18; Fanout = 1; COMB Node = 'outdata\[20\]~220'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[19]~219 outdata[20]~220 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 3.604 ns outdata\[21\]~187 23 COMB LCCOMB_X27_Y5_N20 1 " "Info: 23: + IC(0.000 ns) + CELL(0.506 ns) = 3.604 ns; Loc. = LCCOMB_X27_Y5_N20; Fanout = 1; COMB Node = 'outdata\[21\]~187'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.506 ns" { outdata[20]~220 outdata[21]~187 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.712 ns outdata\[21\] 24 REG LCFF_X27_Y5_N21 2 " "Info: 24: + IC(0.000 ns) + CELL(0.108 ns) = 3.712 ns; Loc. = LCFF_X27_Y5_N21; Fanout = 2; REG Node = 'outdata\[21\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { outdata[21]~187 outdata[21] } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.252 ns ( 87.61 % ) " "Info: Total cell delay = 3.252 ns ( 87.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.460 ns ( 12.39 % ) " "Info: Total interconnect delay = 0.460 ns ( 12.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.712 ns" { outdata[0] outdata[0]~200 outdata[1]~201 outdata[2]~202 outdata[3]~203 outdata[4]~204 outdata[5]~205 outdata[6]~206 outdata[7]~207 outdata[8]~208 outdata[9]~209 outdata[10]~210 outdata[11]~211 outdata[12]~212 outdata[13]~213 outdata[14]~214 outdata[15]~215 outdata[16]~216 outdata[17]~217 outdata[18]~218 outdata[19]~219 outdata[20]~220 outdata[21]~187 outdata[21] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.712 ns" { outdata[0] outdata[0]~200 outdata[1]~201 outdata[2]~202 outdata[3]~203 outdata[4]~204 outdata[5]~205 outdata[6]~206 outdata[7]~207 outdata[8]~208 outdata[9]~209 outdata[10]~210 outdata[11]~211 outdata[12]~212 outdata[13]~213 outdata[14]~214 outdata[15]~215 outdata[16]~216 outdata[17]~217 outdata[18]~218 outdata[19]~219 outdata[20]~220 outdata[21]~187 outdata[21] } { 0.000ns 0.460ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.506ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.012 ns - Smallest " "Info: - Smallest clock skew is 0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.748 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.748 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 2.748 ns outdata\[21\] 3 REG LCFF_X27_Y5_N21 2 " "Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.748 ns; Loc. = LCFF_X27_Y5_N21; Fanout = 2; REG Node = 'outdata\[21\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.505 ns" { clk~clkctrl outdata[21] } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 64.26 % ) " "Info: Total cell delay = 1.766 ns ( 64.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.982 ns ( 35.74 % ) " "Info: Total interconnect delay = 0.982 ns ( 35.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.748 ns" { clk clk~clkctrl outdata[21] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.748 ns" { clk clk~combout clk~clkctrl outdata[21] } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.736 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.827 ns) + CELL(0.666 ns) 2.736 ns outdata\[0\] 3 REG LCFF_X27_Y6_N11 2 " "Info: 3: + IC(0.827 ns) + CELL(0.666 ns) = 2.736 ns; Loc. = LCFF_X27_Y6_N11; Fanout = 2; REG Node = 'outdata\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { clk~clkctrl outdata[0] } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 64.55 % ) " "Info: Total cell delay = 1.766 ns ( 64.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.970 ns ( 35.45 % ) " "Info: Total interconnect delay = 0.970 ns ( 35.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.736 ns" { clk clk~clkctrl outdata[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.736 ns" { clk clk~combout clk~clkctrl outdata[0] } { 0.000ns 0.000ns 0.143ns 0.827ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.748 ns" { clk clk~clkctrl outdata[21] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.748 ns" { clk clk~combout clk~clkctrl outdata[21] } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.736 ns" { clk clk~clkctrl outdata[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.736 ns" { clk clk~combout clk~clkctrl outdata[0] } { 0.000ns 0.000ns 0.143ns 0.827ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.712 ns" { outdata[0] outdata[0]~200 outdata[1]~201 outdata[2]~202 outdata[3]~203 outdata[4]~204 outdata[5]~205 outdata[6]~206 outdata[7]~207 outdata[8]~208 outdata[9]~209 outdata[10]~210 outdata[11]~211 outdata[12]~212 outdata[13]~213 outdata[14]~214 outdata[15]~215 outdata[16]~216 outdata[17]~217 outdata[18]~218 outdata[19]~219 outdata[20]~220 outdata[21]~187 outdata[21] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.712 ns" { outdata[0] outdata[0]~200 outdata[1]~201 outdata[2]~202 outdata[3]~203 outdata[4]~204 outdata[5]~205 outdata[6]~206 outdata[7]~207 outdata[8]~208 outdata[9]~209 outdata[10]~210 outdata[11]~211 outdata[12]~212 outdata[13]~213 outdata[14]~214 outdata[15]~215 outdata[16]~216 outdata[17]~217 outdata[18]~218 outdata[19]~219 outdata[20]~220 outdata[21]~187 outdata[21] } { 0.000ns 0.460ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.506ns 0.108ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.748 ns" { clk clk~clkctrl outdata[21] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.748 ns" { clk clk~combout clk~clkctrl outdata[21] } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.736 ns" { clk clk~clkctrl outdata[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.736 ns" { clk clk~combout clk~clkctrl outdata[0] } { 0.000ns 0.000ns 0.143ns 0.827ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "outdata\[21\] Fword\[2\] clk 7.551 ns register " "Info: tsu for register \"outdata\[21\]\" (data pin = \"Fword\[2\]\", clock pin = \"clk\") is 7.551 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.339 ns + Longest pin register " "Info: + Longest pin to register delay is 10.339 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns Fword\[2\] 1 PIN PIN_112 2 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_112; Fanout = 2; PIN Node = 'Fword\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Fword[2] } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.305 ns) + CELL(0.735 ns) 7.984 ns outdata\[2\]~202 2 COMB LCCOMB_X27_Y6_N14 2 " "Info: 2: + IC(6.305 ns) + CELL(0.735 ns) = 7.984 ns; Loc. = LCCOMB_X27_Y6_N14; Fanout = 2; COMB Node = 'outdata\[2\]~202'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.040 ns" { Fword[2] outdata[2]~202 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.070 ns outdata\[3\]~203 3 COMB LCCOMB_X27_Y6_N16 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 8.070 ns; Loc. = LCCOMB_X27_Y6_N16; Fanout = 2; COMB Node = 'outdata\[3\]~203'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[2]~202 outdata[3]~203 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.156 ns outdata\[4\]~204 4 COMB LCCOMB_X27_Y6_N18 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 8.156 ns; Loc. = LCCOMB_X27_Y6_N18; Fanout = 2; COMB Node = 'outdata\[4\]~204'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[3]~203 outdata[4]~204 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.242 ns outdata\[5\]~205 5 COMB LCCOMB_X27_Y6_N20 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 8.242 ns; Loc. = LCCOMB_X27_Y6_N20; Fanout = 2; COMB Node = 'outdata\[5\]~205'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[4]~204 outdata[5]~205 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.328 ns outdata\[6\]~206 6 COMB LCCOMB_X27_Y6_N22 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 8.328 ns; Loc. = LCCOMB_X27_Y6_N22; Fanout = 2; COMB Node = 'outdata\[6\]~206'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[5]~205 outdata[6]~206 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.414 ns outdata\[7\]~207 7 COMB LCCOMB_X27_Y6_N24 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 8.414 ns; Loc. = LCCOMB_X27_Y6_N24; Fanout = 2; COMB Node = 'outdata\[7\]~207'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[6]~206 outdata[7]~207 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.500 ns outdata\[8\]~208 8 COMB LCCOMB_X27_Y6_N26 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 8.500 ns; Loc. = LCCOMB_X27_Y6_N26; Fanout = 2; COMB Node = 'outdata\[8\]~208'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[7]~207 outdata[8]~208 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.586 ns outdata\[9\]~209 9 COMB LCCOMB_X27_Y6_N28 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 8.586 ns; Loc. = LCCOMB_X27_Y6_N28; Fanout = 2; COMB Node = 'outdata\[9\]~209'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[8]~208 outdata[9]~209 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.175 ns) 8.761 ns outdata\[10\]~210 10 COMB LCCOMB_X27_Y6_N30 2 " "Info: 10: + IC(0.000 ns) + CELL(0.175 ns) = 8.761 ns; Loc. = LCCOMB_X27_Y6_N30; Fanout = 2; COMB Node = 'outdata\[10\]~210'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.175 ns" { outdata[9]~209 outdata[10]~210 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.847 ns outdata\[11\]~211 11 COMB LCCOMB_X27_Y5_N0 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 8.847 ns; Loc. = LCCOMB_X27_Y5_N0; Fanout = 2; COMB Node = 'outdata\[11\]~211'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[10]~210 outdata[11]~211 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.933 ns outdata\[12\]~212 12 COMB LCCOMB_X27_Y5_N2 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 8.933 ns; Loc. = LCCOMB_X27_Y5_N2; Fanout = 2; COMB Node = 'outdata\[12\]~212'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[11]~211 outdata[12]~212 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 9.019 ns outdata\[13\]~213 13 COMB LCCOMB_X27_Y5_N4 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 9.019 ns; Loc. = LCCOMB_X27_Y5_N4; Fanout = 2; COMB Node = 'outdata\[13\]~213'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[12]~212 outdata[13]~213 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 9.105 ns outdata\[14\]~214 14 COMB LCCOMB_X27_Y5_N6 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 9.105 ns; Loc. = LCCOMB_X27_Y5_N6; Fanout = 2; COMB Node = 'outdata\[14\]~214'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[13]~213 outdata[14]~214 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 9.191 ns outdata\[15\]~215 15 COMB LCCOMB_X27_Y5_N8 2 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 9.191 ns; Loc. = LCCOMB_X27_Y5_N8; Fanout = 2; COMB Node = 'outdata\[15\]~215'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[14]~214 outdata[15]~215 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 9.277 ns outdata\[16\]~216 16 COMB LCCOMB_X27_Y5_N10 2 " "Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 9.277 ns; Loc. = LCCOMB_X27_Y5_N10; Fanout = 2; COMB Node = 'outdata\[16\]~216'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[15]~215 outdata[16]~216 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 9.363 ns outdata\[17\]~217 17 COMB LCCOMB_X27_Y5_N12 2 " "Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 9.363 ns; Loc. = LCCOMB_X27_Y5_N12; Fanout = 2; COMB Node = 'outdata\[17\]~217'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[16]~216 outdata[17]~217 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 9.553 ns outdata\[18\]~218 18 COMB LCCOMB_X27_Y5_N14 2 " "Info: 18: + IC(0.000 ns) + CELL(0.190 ns) = 9.553 ns; Loc. = LCCOMB_X27_Y5_N14; Fanout = 2; COMB Node = 'outdata\[18\]~218'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.190 ns" { outdata[17]~217 outdata[18]~218 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 9.639 ns outdata\[19\]~219 19 COMB LCCOMB_X27_Y5_N16 2 " "Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 9.639 ns; Loc. = LCCOMB_X27_Y5_N16; Fanout = 2; COMB Node = 'outdata\[19\]~219'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[18]~218 outdata[19]~219 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 9.725 ns outdata\[20\]~220 20 COMB LCCOMB_X27_Y5_N18 1 " "Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 9.725 ns; Loc. = LCCOMB_X27_Y5_N18; Fanout = 1; COMB Node = 'outdata\[20\]~220'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { outdata[19]~219 outdata[20]~220 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 10.231 ns outdata\[21\]~187 21 COMB LCCOMB_X27_Y5_N20 1 " "Info: 21: + IC(0.000 ns) + CELL(0.506 ns) = 10.231 ns; Loc. = LCCOMB_X27_Y5_N20; Fanout = 1; COMB Node = 'outdata\[21\]~187'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.506 ns" { outdata[20]~220 outdata[21]~187 } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 10.339 ns outdata\[21\] 22 REG LCFF_X27_Y5_N21 2 " "Info: 22: + IC(0.000 ns) + CELL(0.108 ns) = 10.339 ns; Loc. = LCFF_X27_Y5_N21; Fanout = 2; REG Node = 'outdata\[21\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { outdata[21]~187 outdata[21] } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.034 ns ( 39.02 % ) " "Info: Total cell delay = 4.034 ns ( 39.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.305 ns ( 60.98 % ) " "Info: Total interconnect delay = 6.305 ns ( 60.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.339 ns" { Fword[2] outdata[2]~202 outdata[3]~203 outdata[4]~204 outdata[5]~205 outdata[6]~206 outdata[7]~207 outdata[8]~208 outdata[9]~209 outdata[10]~210 outdata[11]~211 outdata[12]~212 outdata[13]~213 outdata[14]~214 outdata[15]~215 outdata[16]~216 outdata[17]~217 outdata[18]~218 outdata[19]~219 outdata[20]~220 outdata[21]~187 outdata[21] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.339 ns" { Fword[2] Fword[2]~combout outdata[2]~202 outdata[3]~203 outdata[4]~204 outdata[5]~205 outdata[6]~206 outdata[7]~207 outdata[8]~208 outdata[9]~209 outdata[10]~210 outdata[11]~211 outdata[12]~212 outdata[13]~213 outdata[14]~214 outdata[15]~215 outdata[16]~216 outdata[17]~217 outdata[18]~218 outdata[19]~219 outdata[20]~220 outdata[21]~187 outdata[21] } { 0.000ns 0.000ns 6.305ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.944ns 0.735ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.506ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.748 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.748 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 2.748 ns outdata\[21\] 3 REG LCFF_X27_Y5_N21 2 " "Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.748 ns; Loc. = LCFF_X27_Y5_N21; Fanout = 2; REG Node = 'outdata\[21\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.505 ns" { clk~clkctrl outdata[21] } "NODE_NAME" } } { "overflow_test.v" "" { Text "E:/EDAFIle/overflow_test/overflow_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 64.26 % ) " "Info: Total cell delay = 1.766 ns ( 64.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.982 ns ( 35.74 % ) " "Info: Total interconnect delay = 0.982 ns ( 35.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.748 ns" { clk clk~clkctrl outdata[21] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.748 ns" { clk clk~combout clk~clkctrl outdata[21] } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.339 ns" { Fword[2] outdata[2]~202 outdata[3]~203 outdata[4]~204 outdata[5]~205 outdata[6]~206 outdata[7]~207 outdata[8]~208 outdata[9]~209 outdata[10]~210 outdata[11]~211 outdata[12]~212 outdata[13]~213 outdata[14]~214 outdata[15]~215 outdata[16]~216 outdata[17]~217 outdata[18]~218 outdata[19]~219 outdata[20]~220 outdata[21]~187 outdata[21] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.339 ns" { Fword[2] Fword[2]~combout outdata[2]~202 outdata[3]~203 outdata[4]~204 outdata[5]~205 outdata[6]~206 outdata[7]~207 outdata[8]~208 outdata[9]~209 outdata[10]~210 outdata[11]~211 outdata[12]~212 outdata[13]~213 outdata[14]~214 outdata[15]~215 outdata[16]~216 outdata[17]~217 outdata[18]~218 outdata[19]~219 outdata[20]~220 outdata[21]~187 outdata[21] } { 0.000ns 0.000ns 6.305ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.944ns 0.735ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.506ns 0.108ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.748 ns" { clk clk~clkctrl outdata[21] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.748 ns" { clk clk~combout clk~clkctrl outdata[21] } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}