shift_mult.tan.rpt

基于ＦＰＧＡ实现移位乘法功能

; N/A   ; None         ; 6.755 ns   ; p[30]~reg0 ; p[30] ; clk        ;
; N/A   ; None         ; 6.748 ns   ; p[25]~reg0 ; p[25] ; clk        ;
; N/A   ; None         ; 6.423 ns   ; p[27]~reg0 ; p[27] ; clk        ;
; N/A   ; None         ; 6.421 ns   ; p[31]~reg0 ; p[31] ; clk        ;
; N/A   ; None         ; 6.419 ns   ; p[29]~reg0 ; p[29] ; clk        ;
+-------+--------------+------------+------------+-------+------------+


+------------------------------------------------------------------------+
; th                                                                     ;
+---------------+-------------+-----------+-------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To        ; To Clock ;
+---------------+-------------+-----------+-------+-----------+----------+
; N/A           ; None        ; 1.843 ns  ; b[5]  ; tempb[5]  ; clk      ;
; N/A           ; None        ; 1.835 ns  ; b[4]  ; tempb[4]  ; clk      ;
; N/A           ; None        ; 1.754 ns  ; b[7]  ; tempb[7]  ; clk      ;
; N/A           ; None        ; 1.594 ns  ; a[6]  ; tempa[6]  ; clk      ;
; N/A           ; None        ; 1.240 ns  ; b[15] ; tempb[15] ; clk      ;
; N/A           ; None        ; 1.228 ns  ; b[11] ; tempb[11] ; clk      ;
; N/A           ; None        ; 1.206 ns  ; a[5]  ; tempa[5]  ; clk      ;
; N/A           ; None        ; 1.077 ns  ; b[10] ; tempb[10] ; clk      ;
; N/A           ; None        ; 1.072 ns  ; a[12] ; tempa[12] ; clk      ;
; N/A           ; None        ; 1.072 ns  ; a[4]  ; tempa[4]  ; clk      ;
; N/A           ; None        ; 1.065 ns  ; a[11] ; tempa[11] ; clk      ;
; N/A           ; None        ; 1.046 ns  ; a[14] ; tempa[14] ; clk      ;
; N/A           ; None        ; 1.031 ns  ; a[15] ; tempa[15] ; clk      ;
; N/A           ; None        ; 0.962 ns  ; a[8]  ; tempa[8]  ; clk      ;
; N/A           ; None        ; 0.923 ns  ; b[9]  ; tempb[9]  ; clk      ;
; N/A           ; None        ; 0.858 ns  ; b[12] ; tempb[12] ; clk      ;
; N/A           ; None        ; 0.844 ns  ; a[3]  ; tempa[3]  ; clk      ;
; N/A           ; None        ; 0.795 ns  ; b[6]  ; tempb[6]  ; clk      ;
; N/A           ; None        ; 0.793 ns  ; b[13] ; tempb[13] ; clk      ;
; N/A           ; None        ; 0.771 ns  ; b[16] ; tempb[16] ; clk      ;
; N/A           ; None        ; 0.732 ns  ; b[1]  ; tempb[1]  ; clk      ;
; N/A           ; None        ; 0.713 ns  ; b[2]  ; tempb[2]  ; clk      ;
; N/A           ; None        ; 0.698 ns  ; a[1]  ; tempa[1]  ; clk      ;
; N/A           ; None        ; 0.672 ns  ; a[9]  ; tempa[9]  ; clk      ;
; N/A           ; None        ; 0.655 ns  ; b[3]  ; tempb[3]  ; clk      ;
; N/A           ; None        ; 0.607 ns  ; a[7]  ; tempa[7]  ; clk      ;
; N/A           ; None        ; 0.579 ns  ; b[8]  ; tempb[8]  ; clk      ;
; N/A           ; None        ; 0.579 ns  ; a[13] ; tempa[13] ; clk      ;
; N/A           ; None        ; 0.473 ns  ; b[14] ; tempb[14] ; clk      ;
; N/A           ; None        ; 0.456 ns  ; a[10] ; tempa[10] ; clk      ;
; N/A           ; None        ; 0.406 ns  ; a[2]  ; tempa[2]  ; clk      ;
; N/A           ; None        ; 0.402 ns  ; a[16] ; tempa[16] ; clk      ;
+---------------+-------------+-----------+-------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Jul 19 02:02:59 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shift_mult -c shift_mult --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 131.6 MHz between source register "i[22]" and destination register "tempb[6]" (period= 7.599 ns)
    Info: + Longest register to register delay is 7.338 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y3_N6; Fanout = 4; REG Node = 'i[22]'
        Info: 2: + IC(0.746 ns) + CELL(0.590 ns) = 1.336 ns; Loc. = LC_X18_Y3_N4; Fanout = 1; COMB Node = 'Equal0~323'
        Info: 3: + IC(1.253 ns) + CELL(0.292 ns) = 2.881 ns; Loc. = LC_X17_Y2_N7; Fanout = 21; COMB Node = 'Equal0~325'
        Info: 4: + IC(0.448 ns) + CELL(0.292 ns) = 3.621 ns; Loc. = LC_X17_Y2_N9; Fanout = 4; COMB Node = 'LessThan0~288'
        Info: 5: + IC(1.262 ns) + CELL(0.292 ns) = 5.175 ns; Loc. = LC_X16_Y5_N9; Fanout = 48; COMB Node = 'tempa[17]~2572'
        Info: 6: + IC(1.296 ns) + CELL(0.867 ns) = 7.338 ns; Loc. = LC_X19_Y5_N7; Fanout = 1; REG Node = 'tempb[6]'
        Info: Total cell delay = 2.333 ns ( 31.79 % )
        Info: Total interconnect delay = 5.005 ns ( 68.21 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.743 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 144; CLK Node = 'clk'
            Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X19_Y5_N7; Fanout = 1; REG Node = 'tempb[6]'
            Info: Total cell delay = 2.180 ns ( 79.48 % )
            Info: Total interconnect delay = 0.563 ns ( 20.52 % )
        Info: - Longest clock path from clock "clk" to source register is 2.743 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 144; CLK Node = 'clk'
            Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X17_Y3_N6; Fanout = 4; REG Node = 'i[22]'
            Info: Total cell delay = 2.180 ns ( 79.48 % )
            Info: Total interconnect delay = 0.563 ns ( 20.52 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "tempa[16]" (data pin = "a[16]", clock pin = "clk") is -0.350 ns
    Info: + Longest pin to register delay is 2.395 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y7_N2; Fanout = 1; PIN Node = 'a[16]'
        Info: 2: + IC(1.657 ns) + CELL(0.738 ns) = 2.395 ns; Loc. = LC_X15_Y6_N4; Fanout = 3; REG Node = 'tempa[16]'
        Info: Total cell delay = 0.738 ns ( 30.81 % )
        Info: Total interconnect delay = 1.657 ns ( 69.19 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.782 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 144; CLK Node =