shift_mult.tan.qmsg

基于ＦＰＧＡ实现移位乘法功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 19 02:02:59 2007 " "Info: Processing started: Thu Jul 19 02:02:59 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off shift_mult -c shift_mult --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shift_mult -c shift_mult --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "shift_mult.v" "" { Text "E:/EDAFIle/shift_mult_16/shift_mult.v" 3 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register i\[22\] register tempb\[6\] 131.6 MHz 7.599 ns Internal " "Info: Clock \"clk\" has Internal fmax of 131.6 MHz between source register \"i\[22\]\" and destination register \"tempb\[6\]\" (period= 7.599 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.338 ns + Longest register register " "Info: + Longest register to register delay is 7.338 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i\[22\] 1 REG LC_X17_Y3_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y3_N6; Fanout = 4; REG Node = 'i\[22\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { i[22] } "NODE_NAME" } } { "shift_mult.v" "" { Text "E:/EDAFIle/shift_mult_16/shift_mult.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.746 ns) + CELL(0.590 ns) 1.336 ns Equal0~323 2 COMB LC_X18_Y3_N4 1 " "Info: 2: + IC(0.746 ns) + CELL(0.590 ns) = 1.336 ns; Loc. = LC_X18_Y3_N4; Fanout = 1; COMB Node = 'Equal0~323'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.336 ns" { i[22] Equal0~323 } "NODE_NAME" } } { "shift_mult.v" "" { Text "E:/EDAFIle/shift_mult_16/shift_mult.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.253 ns) + CELL(0.292 ns) 2.881 ns Equal0~325 3 COMB LC_X17_Y2_N7 21 " "Info: 3: + IC(1.253 ns) + CELL(0.292 ns) = 2.881 ns; Loc. = LC_X17_Y2_N7; Fanout = 21; COMB Node = 'Equal0~325'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.545 ns" { Equal0~323 Equal0~325 } "NODE_NAME" } } { "shift_mult.v" "" { Text "E:/EDAFIle/shift_mult_16/shift_mult.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.292 ns) 3.621 ns LessThan0~288 4 COMB LC_X17_Y2_N9 4 " "Info: 4: + IC(0.448 ns) + CELL(0.292 ns) = 3.621 ns; Loc. = LC_X17_Y2_N9; Fanout = 4; COMB Node = 'LessThan0~288'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.740 ns" { Equal0~325 LessThan0~288 } "NODE_NAME" } } { "shift_mult.v" "" { Text "E:/EDAFIle/shift_mult_16/shift_mult.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.262 ns) + CELL(0.292 ns) 5.175 ns tempa\[17\]~2572 5 COMB LC_X16_Y5_N9 48 " "Info: 5: + IC(1.262 ns) + CELL(0.292 ns) = 5.175 ns; Loc. = LC_X16_Y5_N9; Fanout = 48; COMB Node = 'tempa\[17\]~2572'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.554 ns" { LessThan0~288 tempa[17]~2572 } "NODE_NAME" } } { "shift_mult.v" "" { Text "E:/EDAFIle/shift_mult_16/shift_mult.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.296 ns) + CELL(0.867 ns) 7.338 ns tempb\[6\] 6 REG LC_X19_Y5_N7 1 " "Info: 6: + IC(1.296 ns) + CELL(0.867 ns) = 7.338 ns; Loc. = LC_X19_Y5_N7; Fanout = 1; REG Node = 'tempb\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.163 ns" { tempa[17]~2572 tempb[6] } "NODE_NAME" } } { "shift_mult.v" "" { Text "E:/EDAFIle/shift_mult_16/shift_mult.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.333 ns ( 31.79 % ) " "Info: Total cell delay = 2.333 ns ( 31.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.005 ns ( 68.21 % ) " "Info: Total interconnect delay = 5.005 ns ( 68.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.338 ns" { i[22] Equal0~323 Equal0~325 LessThan0~288 tempa[17]~2572 tempb[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.338 ns" { i[22] Equal0~323 Equal0~325 LessThan0~288 tempa[17]~2572 tempb[6] } { 0.000ns 0.746ns 1.253ns 0.448ns 1.262ns 1.296ns } { 0.000ns 0.590ns 0.292ns 0.292ns 0.292ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.743 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 144 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 144; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "shift_mult.v" "" { Text "E:/EDAFIle/shift_mult_16/shift_mult.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns tempb\[6\] 2 REG LC_X19_Y5_N7 1 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X19_Y5_N7; Fanout = 1; REG Node = 'tempb\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.274 ns" { clk tempb[6] } "NODE_NAME" } } { "shift_mult.v" "" { Text "E:/EDAFIle/shift_mult_16/shift_mult.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.48 % ) " "Info: Total cell delay = 2.180 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clk tempb[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 tempb[6] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.743 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 144 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 144; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "shift_mult.v" "" { Text "E:/EDAFIle/shift_mult_16/shift_mult.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns i\[22\] 2 REG LC_X17_Y3_N6 4 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X17_Y3_N6; Fanout = 4; REG Node = 'i\[22\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.274 ns" { clk i[22] } "NODE_NAME" } } { "shift_mult.v" "" { Text "E:/EDAFIle/shift_mult_16/shift_mult.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.48 % ) " "Info: Total cell delay = 2.180 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clk i[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 i[22] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clk tempb[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 tempb[6] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clk i[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 i[22] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "shift_mult.v" "" { Text "E:/EDAFIle/shift_mult_16/shift_mult.v" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "shift_mult.v" "" { Text "E:/EDAFIle/shift_mult_16/shift_mult.v" 27 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.338 ns" { i[22] Equal0~323 Equal0~325 LessThan0~288 tempa[17]~2572 tempb[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.338 ns" { i[22] Equal0~323 Equal0~325 LessThan0~288 tempa[17]~2572 tempb[6] } { 0.000ns 0.746ns 1.253ns 0.448ns 1.262ns 1.296ns } { 0.000ns 0.590ns 0.292ns 0.292ns 0.292ns 0.867ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clk tempb[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 tempb[6] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clk i[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 i[22] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}