dds.v

来自「基于ＦＰＧＡ平台」· Verilog 代码 · 共 57 行

module DDS(
    clk,
    Fword,
    Pword,
    Fout
);

input clk;
input [7:0]Fword;
input [7:0]Pword;
output [9:0]Fout;

wire [31:0]Fword32B;
wire [31:0]SYNTHESIZED_WIRE_1;
wire [31:0]SYNTHESIZED_WIRE_2;
wire [31:0]SYNTHESIZED_WIRE_3;
wire [9:0]Pword10B;
wire [9:0]SYNTHESIZED_WIRE_4;
wire [9:0]SYNTHESIZED_WIRE_5;

assign Fword32B[31:28]=4'b0000;
assign Fword32B[19:0]=20'h0000;
assign Pword10B[1:0]=2'b00;
assign Fword32B[27:20]=Fword;
assign Pword10B[9:2]=Pword;

REG32B     U1(.Load(clk),
              .Din(Fword32B),
              .Dout(SYNTHESIZED_WIRE_1));
defparam   U1.size = 32;

Adder32B   U2(.A(SYNTHESIZED_WIRE_1),
              .B(SYNTHESIZED_WIRE_2),
              .S(SYNTHESIZED_WIRE_3));
defparam   U2.size = 32;

REG32B     U3(.Load(clk),
              .Din(SYNTHESIZED_WIRE_3),
              .Dout(SYNTHESIZED_WIRE_2));
defparam   U3.size = 32;

Adder10B   U4(.A(Pword10B),
              .B(SYNTHESIZED_WIRE_2[31:22]),
              .S(SYNTHESIZED_WIRE_4));
defparam   U4.size = 10;

REG10B     U5(.Load(clk),
              .Din(SYNTHESIZED_WIRE_4),
              .Dout(SYNTHESIZED_WIRE_5));
defparam   U5.size = 10;

Sin_rom    U6(.clock(clk),
              .address(SYNTHESIZED_WIRE_5),
	          .q(Fout));


endmodule