dds.hier_info

基于ＦＰＧＡ平台

A[2] => Add0.IN8
A[3] => Add0.IN7
A[4] => Add0.IN6
A[5] => Add0.IN5
A[6] => Add0.IN4
A[7] => Add0.IN3
A[8] => Add0.IN2
A[9] => Add0.IN1
B[0] => Add0.IN20
B[1] => Add0.IN19
B[2] => Add0.IN18
B[3] => Add0.IN17
B[4] => Add0.IN16
B[5] => Add0.IN15
B[6] => Add0.IN14
B[7] => Add0.IN13
B[8] => Add0.IN12
B[9] => Add0.IN11
S[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE


|DDS|REG10B:U5
Load => Dout[8]~reg0.CLK
Load => Dout[7]~reg0.CLK
Load => Dout[6]~reg0.CLK
Load => Dout[5]~reg0.CLK
Load => Dout[4]~reg0.CLK
Load => Dout[3]~reg0.CLK
Load => Dout[2]~reg0.CLK
Load => Dout[1]~reg0.CLK
Load => Dout[0]~reg0.CLK
Load => Dout[9]~reg0.CLK
Din[0] => Dout[0]~reg0.DATAIN
Din[1] => Dout[1]~reg0.DATAIN
Din[2] => Dout[2]~reg0.DATAIN
Din[3] => Dout[3]~reg0.DATAIN
Din[4] => Dout[4]~reg0.DATAIN
Din[5] => Dout[5]~reg0.DATAIN
Din[6] => Dout[6]~reg0.DATAIN
Din[7] => Dout[7]~reg0.DATAIN
Din[8] => Dout[8]~reg0.DATAIN
Din[9] => Dout[9]~reg0.DATAIN
Dout[0] <= Dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[1] <= Dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[2] <= Dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[3] <= Dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[4] <= Dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[5] <= Dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[6] <= Dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[7] <= Dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[8] <= Dout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[9] <= Dout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DDS|Sin_rom:U6
address[0] => address[0]~9.IN1
address[1] => address[1]~8.IN1
address[2] => address[2]~7.IN1
address[3] => address[3]~6.IN1
address[4] => address[4]~5.IN1
address[5] => address[5]~4.IN1
address[6] => address[6]~3.IN1
address[7] => address[7]~2.IN1
address[8] => address[8]~1.IN1
address[9] => address[9]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
q[8] <= altsyncram:altsyncram_component.q_a
q[9] <= altsyncram:altsyncram_component.q_a


|DDS|Sin_rom:U6|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_ha91:auto_generated.address_a[0]
address_a[1] => altsyncram_ha91:auto_generated.address_a[1]
address_a[2] => altsyncram_ha91:auto_generated.address_a[2]
address_a[3] => altsyncram_ha91:auto_generated.address_a[3]
address_a[4] => altsyncram_ha91:auto_generated.address_a[4]
address_a[5] => altsyncram_ha91:auto_generated.address_a[5]
address_a[6] => altsyncram_ha91:auto_generated.address_a[6]
address_a[7] => altsyncram_ha91:auto_generated.address_a[7]
address_a[8] => altsyncram_ha91:auto_generated.address_a[8]
address_a[9] => altsyncram_ha91:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_ha91:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_ha91:auto_generated.q_a[0]
q_a[1] <= altsyncram_ha91:auto_generated.q_a[1]
q_a[2] <= altsyncram_ha91:auto_generated.q_a[2]
q_a[3] <= altsyncram_ha91:auto_generated.q_a[3]
q_a[4] <= altsyncram_ha91:auto_generated.q_a[4]
q_a[5] <= altsyncram_ha91:auto_generated.q_a[5]
q_a[6] <= altsyncram_ha91:auto_generated.q_a[6]
q_a[7] <= altsyncram_ha91:auto_generated.q_a[7]
q_a[8] <= altsyncram_ha91:auto_generated.q_a[8]
q_a[9] <= altsyncram_ha91:auto_generated.q_a[9]
q_b[0] <= <GND>


|DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated
address_a[0] => altsyncram_66f2:altsyncram1.address_a[0]
address_a[1] => altsyncram_66f2:altsyncram1.address_a[1]
address_a[2] => altsyncram_66f2:altsyncram1.address_a[2]
address_a[3] => altsyncram_66f2:altsyncram1.address_a[3]
address_a[4] => altsyncram_66f2:altsyncram1.address_a[4]
address_a[5] => altsyncram_66f2:altsyncram1.address_a[5]
address_a[6] => altsyncram_66f2:altsyncram1.address_a[6]
address_a[7] => altsyncram_66f2:altsyncram1.address_a[7]
address_a[8] => altsyncram_66f2:altsyncram1.address_a[8]
address_a[9] => altsyncram_66f2:altsyncram1.address_a[9]
clock0 => altsyncram_66f2:altsyncram1.clock0
q_a[0] <= altsyncram_66f2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_66f2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_66f2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_66f2:altsyncram1.q_a[3]
q_a[4] <= altsyncram_66f2:altsyncram1.q_a[4]
q_a[5] <= altsyncram_66f2:altsyncram1.q_a[5]
q_a[6] <= altsyncram_66f2:altsyncram1.q_a[6]
q_a[7] <= altsyncram_66f2:altsyncram1.q_a[7]
q_a[8] <= altsyncram_66f2:altsyncram1.q_a[8]
q_a[9] <= altsyncram_66f2:altsyncram1.q_a[9]


|DDS|Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[0] => ram_block3a8.PORTAADDR
address_a[0] => ram_block3a9.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[1] => ram_block3a8.PORTAADDR1
address_a[1] => ram_block3a9.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[2] => ram_block3a8.PORTAADDR2
address_a[2] => ram_block3a9.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[3] => ram_block3a8.PORTAADDR3
address_a[3] => ram_block3a9.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[4] => ram_block3a8.PORTAADDR4
address_a[4] => ram_block3a9.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[5] => ram_block3a8.PORTAADDR5
address_a[5] => ram_block3a9.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[6] => ram_block3a8.PORTAADDR6
address_a[6] => ram_block3a9.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_a[7] => ram_block3a8.PORTAADDR7
address_a[7] => ram_block3a9.PORTAADDR7
address_a[8] => ram_block3a0.PORTAADDR8
address_a[8] => ram_block3a1.PORTAADDR8
address_a[8] => ram_block3a2.PORTAADDR8
address_a[8] => ram_block3a3.PORTAADDR8
address_a[8] => ram_block3a4.PORTAADDR8
address_a[8] => ram_block3a5.PORTAADDR8
address_a[8] => ram_block3a6.PORTAADDR8
address_a[8] => ram_block3a7.PORTAADDR8
address_a[8] => ram_block3a8.PORTAADDR8
address_a[8] => ram_block3a9.PORTAADDR8
address_a[9] => ram_block3a0.PORTAADDR9
address_a[9] => ram_block3a1.PORTAADDR9
address_a[9] => ram_block3a2.PORTAADDR9
address_a[9] => ram_block3a3.PORTAADDR9
address_a[9] => ram_block3a4.PORTAADDR9
address_a[9] => ram_block3a5.PORTAADDR9
address_a[9] => ram_block3a6.PORTAADDR9
address_a[9] => ram_block3a7.PORTAADDR9
address_a[9] => ram_block3a8.PORTAADDR9
address_a[9] => ram_block3a9.PORTAADDR9
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[0] => ram_block3a8.PORTBADDR
address_b[0] => ram_block3a9.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[1] => ram_block3a8.PORTBADDR1
address_b[1] => ram_block3a9.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2
address_b[2] => ram_block3a7.PORTBADDR2
address_b[2] => ram_block3a8.PORTBADDR2
address_b[2] => ram_block3a9.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[3] => ram_block3a4.PORTBADDR3
address_b[3] => ram_block3a5.PORTBADDR3
address_b[3] => ram_block3a6.PORTBADDR3
address_b[3] => ram_block3a7.PORTBADDR3
address_b[3] => ram_block3a8.PORTBADDR3
address_b[3] => ram_block3a9.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[4] => ram_block3a4.PORTBADDR4
address_b[4] => ram_block3a5.PORTBADDR4
address_b[4] => ram_block3a6.PORTBADDR4
address_b[4] => ram_block3a7.PORTBADDR4
address_b[4] => ram_block3a8.PORTBADDR4
address_b[4] => ram_block3a9.PORTBADDR4
address_b[5] => ram_block3a0.PORTBADDR5
address_b[5] => ram_block3a1.PORTBADDR5
address_b[5] => ram_block3a2.PORTBADDR5
address_b[5] => ram_block3a3.PORTBADDR5
address_b[5] => ram_block3a4.PORTBADDR5
address_b[5] => ram_block3a5.PORTBADDR5
address_b[5] => ram_block3a6.PORTBADDR5
address_b[5] => ram_block3a7.PORTBADDR5
address_b[5] => ram_block3a8.PORTBADDR5
address_b[5] => ram_block3a9.PORTBADDR5
address_b[6] => ram_block3a0.PORTBADDR6
address_b[6] => ram_block3a1.PORTBADDR6
address_b[6] => ram_block3a2.PORTBADDR6
address_b[6] => ram_block3a3.PORTBADDR6
address_b[6] => ram_block3a4.PORTBADDR6
address_b[6] => ram_block3a5.PORTBADDR6
address_b[6] => ram_block3a6.PORTBADDR6
address_b[6] => ram_block3a7.PORTBADDR6
address_b[6] => ram_block3a8.PORTBADDR6