dds.fit.qmsg

基于ＦＰＧＡ平台

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.795 ns register register " "Info: Estimated most critical path is register to register delay of 6.795 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode 1 REG LAB_X18_Y6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X18_Y6; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 392 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.944 ns) + CELL(0.646 ns) 1.590 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|name_gen~33 2 COMB LAB_X19_Y5 8 " "Info: 2: + IC(0.944 ns) + CELL(0.646 ns) = 1.590 ns; Loc. = LAB_X19_Y5; Fanout = 8; COMB Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|name_gen~33'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.590 ns" { sld_hub:sld_hub_inst|jtag_debug_mode Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|name_gen~33 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.624 ns) 3.481 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_incr_addr~31 3 COMB LAB_X22_Y6 1 " "Info: 3: + IC(1.267 ns) + CELL(0.624 ns) = 3.481 ns; Loc. = LAB_X22_Y6; Fanout = 1; COMB Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_incr_addr~31'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.891 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|name_gen~33 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~31 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.651 ns) 4.292 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_incr_addr 4 COMB LAB_X22_Y6 2 " "Info: 4: + IC(0.160 ns) + CELL(0.651 ns) = 4.292 ns; Loc. = LAB_X22_Y6; Fanout = 2; COMB Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_incr_addr'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.811 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~31 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.596 ns) 5.493 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~130 5 COMB LAB_X22_Y6 2 " "Info: 5: + IC(0.605 ns) + CELL(0.596 ns) = 5.493 ns; Loc. = LAB_X22_Y6; Fanout = 2; COMB Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~130'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.201 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~130 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.579 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\]~131 6 COMB LAB_X22_Y6 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 5.579 ns; Loc. = LAB_X22_Y6; Fanout = 2; COMB Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\]~131'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~130 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~131 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.665 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\]~132 7 COMB LAB_X22_Y6 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 5.665 ns; Loc. = LAB_X22_Y6; Fanout = 2; COMB Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\]~132'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~131 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~132 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.751 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\]~133 8 COMB LAB_X22_Y6 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 5.751 ns; Loc. = LAB_X22_Y6; Fanout = 2; COMB Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\]~133'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~132 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~133 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.837 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\]~134 9 COMB LAB_X22_Y6 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 5.837 ns; Loc. = LAB_X22_Y6; Fanout = 2; COMB Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\]~134'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~133 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~134 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.923 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[5\]~135 10 COMB LAB_X22_Y6 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 5.923 ns; Loc. = LAB_X22_Y6; Fanout = 2; COMB Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[5\]~135'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~134 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]~135 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 6.009 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[6\]~136 11 COMB LAB_X22_Y6 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 6.009 ns; Loc. = LAB_X22_Y6; Fanout = 2; COMB Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[6\]~136'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]~135 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]~136 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 6.095 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[7\]~137 12 COMB LAB_X22_Y6 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 6.095 ns; Loc. = LAB_X22_Y6; Fanout = 2; COMB Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[7\]~137'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]~136 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]~137 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 6.181 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[8\]~138 13 COMB LAB_X22_Y6 1 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 6.181 ns; Loc. = LAB_X22_Y6; Fanout = 1; COMB Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[8\]~138'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]~137 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]~138 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 6.687 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[9\]~129 14 COMB LAB_X22_Y6 1 " "Info: 14: + IC(0.000 ns) + CELL(0.506 ns) = 6.687 ns; Loc. = LAB_X22_Y6; Fanout = 1; COMB Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[9\]~129'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.506 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]~138 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9]~129 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.795 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[9\] 15 REG LAB_X22_Y6 12 " "Info: 15: + IC(0.000 ns) + CELL(0.108 ns) = 6.795 ns; Loc. = LAB_X22_Y6; Fanout = 12; REG Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[9\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9]~129 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9] } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.819 ns ( 56.20 % ) " "Info: Total cell delay = 3.819 ns ( 56.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.976 ns ( 43.80 % ) " "Info: Total interconnect delay = 2.976 ns ( 43.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.795 ns" { sld_hub:sld_hub_inst|jtag_debug_mode Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|name_gen~33 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~31 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~130 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~131 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~132 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~133 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~134 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]~135 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]~136 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]~137 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]~138 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9]~129 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "