dds.fit.qmsg

基于ＦＰＧＡ平台

{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0  " "Info: Automatically promoted node Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process1~1 " "Info: Destination node Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process1~1" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process1~1" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|process1~1 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|process1~1 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process0~11 " "Info: Destination node Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process0~11" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process0~11" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|process0~11 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|process0~11 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~13 " "Info: Destination node Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~13" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~13" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~13 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~13 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}