dds.tan.qmsg

基于ＦＰＧＡ平台

{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[14\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP 1.979 ns register " "Info: th for register \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[14\]\" (data pin = \"altera_internal_jtag~TMSUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 1.979 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.297 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.297 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y7_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y7_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.811 ns) + CELL(0.000 ns) 3.811 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G1 162 " "Info: 2: + IC(3.811 ns) + CELL(0.000 ns) = 3.811 ns; Loc. = CLKCTRL_G1; Fanout = 162; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.811 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.820 ns) + CELL(0.666 ns) 5.297 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[14\] 3 REG LCFF_X20_Y6_N5 2 " "Info: 3: + IC(0.820 ns) + CELL(0.666 ns) = 5.297 ns; Loc. = LCFF_X20_Y6_N5; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[14\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.486 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14] } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 12.57 % ) " "Info: Total cell delay = 0.666 ns ( 12.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.631 ns ( 87.43 % ) " "Info: Total interconnect delay = 4.631 ns ( 87.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.297 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.297 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14] } { 0.000ns 3.811ns 0.820ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.624 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.624 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y7_N0 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y7_N0; Fanout = 23; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.310 ns) + CELL(0.206 ns) 3.516 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~28 2 COMB LCCOMB_X20_Y6_N4 1 " "Info: 2: + IC(3.310 ns) + CELL(0.206 ns) = 3.516 ns; Loc. = LCCOMB_X20_Y6_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~28'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.516 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~28 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.624 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[14\] 3 REG LCFF_X20_Y6_N5 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 3.624 ns; Loc. = LCFF_X20_Y6_N5; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[14\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~28 sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14] } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 8.66 % ) " "Info: Total cell delay = 0.314 ns ( 8.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.310 ns ( 91.34 % ) " "Info: Total interconnect delay = 3.310 ns ( 91.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.624 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~28 sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.624 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~28 sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14] } { 0.000ns 3.310ns 0.000ns } { 0.000ns 0.206ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.297 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.297 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14] } { 0.000ns 3.811ns 0.820ns } { 0.000ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.624 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~28 sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.624 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~28 sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14] } { 0.000ns 3.310ns 0.000ns } { 0.000ns 0.206ns 0.108ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 21 01:14:16 2007 " "Info: Processing ended: Thu Jun 21 01:14:16 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}