dds.tan.qmsg

基于ＦＰＧＡ平台

{ "Info" "ITDB_TSU_RESULT" "REG10B:U5\|Dout\[9\] Pword\[1\] clk 6.038 ns register " "Info: tsu for register \"REG10B:U5\|Dout\[9\]\" (data pin = \"Pword\[1\]\", clock pin = \"clk\") is 6.038 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.825 ns + Longest pin register " "Info: + Longest pin to register delay is 8.825 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.965 ns) 0.965 ns Pword\[1\] 1 PIN PIN_74 2 " "Info: 1: + IC(0.000 ns) + CELL(0.965 ns) = 0.965 ns; Loc. = PIN_74; Fanout = 2; PIN Node = 'Pword\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Pword[1] } "NODE_NAME" } } { "DDS.v" "" { Text "E:/EDAFIle/DDS1/DDS.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.081 ns) + CELL(0.735 ns) 7.781 ns REG10B:U5\|Dout\[3\]~51 2 COMB LCCOMB_X24_Y5_N14 2 " "Info: 2: + IC(6.081 ns) + CELL(0.735 ns) = 7.781 ns; Loc. = LCCOMB_X24_Y5_N14; Fanout = 2; COMB Node = 'REG10B:U5\|Dout\[3\]~51'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.816 ns" { Pword[1] REG10B:U5|Dout[3]~51 } "NODE_NAME" } } { "REG10B.v" "" { Text "E:/EDAFIle/DDS1/REG10B.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 7.867 ns REG10B:U5\|Dout\[4\]~52 3 COMB LCCOMB_X24_Y5_N16 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 7.867 ns; Loc. = LCCOMB_X24_Y5_N16; Fanout = 2; COMB Node = 'REG10B:U5\|Dout\[4\]~52'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG10B:U5|Dout[3]~51 REG10B:U5|Dout[4]~52 } "NODE_NAME" } } { "REG10B.v" "" { Text "E:/EDAFIle/DDS1/REG10B.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 7.953 ns REG10B:U5\|Dout\[5\]~53 4 COMB LCCOMB_X24_Y5_N18 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 7.953 ns; Loc. = LCCOMB_X24_Y5_N18; Fanout = 2; COMB Node = 'REG10B:U5\|Dout\[5\]~53'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG10B:U5|Dout[4]~52 REG10B:U5|Dout[5]~53 } "NODE_NAME" } } { "REG10B.v" "" { Text "E:/EDAFIle/DDS1/REG10B.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.039 ns REG10B:U5\|Dout\[6\]~54 5 COMB LCCOMB_X24_Y5_N20 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 8.039 ns; Loc. = LCCOMB_X24_Y5_N20; Fanout = 2; COMB Node = 'REG10B:U5\|Dout\[6\]~54'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG10B:U5|Dout[5]~53 REG10B:U5|Dout[6]~54 } "NODE_NAME" } } { "REG10B.v" "" { Text "E:/EDAFIle/DDS1/REG10B.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.125 ns REG10B:U5\|Dout\[7\]~55 6 COMB LCCOMB_X24_Y5_N22 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 8.125 ns; Loc. = LCCOMB_X24_Y5_N22; Fanout = 2; COMB Node = 'REG10B:U5\|Dout\[7\]~55'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG10B:U5|Dout[6]~54 REG10B:U5|Dout[7]~55 } "NODE_NAME" } } { "REG10B.v" "" { Text "E:/EDAFIle/DDS1/REG10B.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.211 ns REG10B:U5\|Dout\[8\]~56 7 COMB LCCOMB_X24_Y5_N24 1 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 8.211 ns; Loc. = LCCOMB_X24_Y5_N24; Fanout = 1; COMB Node = 'REG10B:U5\|Dout\[8\]~56'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG10B:U5|Dout[7]~55 REG10B:U5|Dout[8]~56 } "NODE_NAME" } } { "REG10B.v" "" { Text "E:/EDAFIle/DDS1/REG10B.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 8.717 ns REG10B:U5\|Dout\[9\]~49 8 COMB LCCOMB_X24_Y5_N26 1 " "Info: 8: + IC(0.000 ns) + CELL(0.506 ns) = 8.717 ns; Loc. = LCCOMB_X24_Y5_N26; Fanout = 1; COMB Node = 'REG10B:U5\|Dout\[9\]~49'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.506 ns" { REG10B:U5|Dout[8]~56 REG10B:U5|Dout[9]~49 } "NODE_NAME" } } { "REG10B.v" "" { Text "E:/EDAFIle/DDS1/REG10B.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.825 ns REG10B:U5\|Dout\[9\] 9 REG LCFF_X24_Y5_N27 3 " "Info: 9: + IC(0.000 ns) + CELL(0.108 ns) = 8.825 ns; Loc. = LCFF_X24_Y5_N27; Fanout = 3; REG Node = 'REG10B:U5\|Dout\[9\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { REG10B:U5|Dout[9]~49 REG10B:U5|Dout[9] } "NODE_NAME" } } { "REG10B.v" "" { Text "E:/EDAFIle/DDS1/REG10B.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.744 ns ( 31.09 % ) " "Info: Total cell delay = 2.744 ns ( 31.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.081 ns ( 68.91 % ) " "Info: Total interconnect delay = 6.081 ns ( 68.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.825 ns" { Pword[1] REG10B:U5|Dout[3]~51 REG10B:U5|Dout[4]~52 REG10B:U5|Dout[5]~53 REG10B:U5|Dout[6]~54 REG10B:U5|Dout[7]~55 REG10B:U5|Dout[8]~56 REG10B:U5|Dout[9]~49 REG10B:U5|Dout[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.825 ns" { Pword[1] Pword[1]~combout REG10B:U5|Dout[3]~51 REG10B:U5|Dout[4]~52 REG10B:U5|Dout[5]~53 REG10B:U5|Dout[6]~54 REG10B:U5|Dout[7]~55 REG10B:U5|Dout[8]~56 REG10B:U5|Dout[9]~49 REG10B:U5|Dout[9] } { 0.000ns 0.000ns 6.081ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.965ns 0.735ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "REG10B.v" "" { Text "E:/EDAFIle/DDS1/REG10B.v" 10 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.747 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.747 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "DDS.v" "" { Text "E:/EDAFIle/DDS1/DDS.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns clk~clkctrl 2 COMB CLKCTRL_G2 70 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "DDS.v" "" { Text "E:/EDAFIle/DDS1/DDS.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.838 ns) + CELL(0.666 ns) 2.747 ns REG10B:U5\|Dout\[9\] 3 REG LCFF_X24_Y5_N27 3 " "Info: 3: + IC(0.838 ns) + CELL(0.666 ns) = 2.747 ns; Loc. = LCFF_X24_Y5_N27; Fanout = 3; REG Node = 'REG10B:U5\|Dout\[9\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.504 ns" { clk~clkctrl REG10B:U5|Dout[9] } "NODE_NAME" } } { "REG10B.v" "" { Text "E:/EDAFIle/DDS1/REG10B.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 64.29 % ) " "Info: Total cell delay = 1.766 ns ( 64.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.981 ns ( 35.71 % ) " "Info: Total interconnect delay = 0.981 ns ( 35.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.747 ns" { clk clk~clkctrl REG10B:U5|Dout[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.747 ns" { clk clk~combout clk~clkctrl REG10B:U5|Dout[9] } { 0.000ns 0.000ns 0.143ns 0.838ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.825 ns" { Pword[1] REG10B:U5|Dout[3]~51 REG10B:U5|Dout[4]~52 REG10B:U5|Dout[5]~53 REG10B:U5|Dout[6]~54 REG10B:U5|Dout[7]~55 REG10B:U5|Dout[8]~56 REG10B:U5|Dout[9]~49 REG10B:U5|Dout[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.825 ns" { Pword[1] Pword[1]~combout REG10B:U5|Dout[3]~51 REG10B:U5|Dout[4]~52 REG10B:U5|Dout[5]~53 REG10B:U5|Dout[6]~54 REG10B:U5|Dout[7]~55 REG10B:U5|Dout[8]~56 REG10B:U5|Dout[9]~49 REG10B:U5|Dout[9] } { 0.000ns 0.000ns 6.081ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.965ns 0.735ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.747 ns" { clk clk~clkctrl REG10B:U5|Dout[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.747 ns" { clk clk~combout clk~clkctrl REG10B:U5|Dout[9] } { 0.000ns 0.000ns 0.143ns 0.838ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Fout\[6\] Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|q_a\[6\] 8.858 ns memory " "Info: tco from clock \"clk\" to destination pin \"Fout\[6\]\" through memory \"Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|q_a\[6\]\" is 8.858 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.828 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 2.828 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "DDS.v" "" { Text "E:/EDAFIle/DDS1/DDS.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns clk~clkctrl 2 COMB CLKCTRL_G2 70 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "DDS.v" "" { Text "E:/EDAFIle/DDS1/DDS.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.770 ns) + CELL(0.815 ns) 2.828 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|q_a\[6\] 3 MEM M4K_X23_Y4 1 " "Info: 3: + IC(0.770 ns) + CELL(0.815 ns) = 2.828 ns; Loc. = M4K_X23_Y4; Fanout = 1; MEM Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|q_a\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.585 ns" { clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[6] } "NODE_NAME" } } { "db/altsyncram_66f2.tdf" "" { Text "E:/EDAFIle/DDS1/db/altsyncram_66f2.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.915 ns ( 67.72 % ) " "Info: Total cell delay = 1.915 ns ( 67.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.913 ns ( 32.28 % ) " "Info: Total interconnect delay = 0.913 ns ( 32.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.828 ns" { clk clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.828 ns" { clk clk~combout clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[6] } { 0.000ns 0.000ns 0.143ns 0.770ns } { 0.000ns 1.100ns 0.000ns 0.815ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_66f2.tdf" "" { Text "E:/EDAFIle/DDS1/db/altsyncram_66f2.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.770 ns + Longest memory pin " "Info: + Longest memory to pin delay is 5.770 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.109 ns) 0.109 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|q_a\[6\] 1 MEM M4K_X23_Y4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X23_Y4; Fanout = 1; MEM Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|q_a\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[6] } "NODE_NAME" } } { "db/altsyncram_66f2.tdf" "" { Text "E:/EDAFIle/DDS1/db/altsyncram_66f2.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.435 ns) + CELL(3.226 ns) 5.770 ns Fout\[6\] 2 PIN PIN_125 0 " "Info: 2: + IC(2.435 ns) + CELL(3.226 ns) = 5.770 ns; Loc. = PIN_125; Fanout = 0; PIN Node = 'Fout\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.661 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[6] Fout[6] } "NODE_NAME" } } { "DDS.v" "" { Text "E:/EDAFIle/DDS1/DDS.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.335 ns ( 57.80 % ) " "Info: Total cell delay = 3.335 ns ( 57.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.435 ns ( 42.20 % ) " "Info: Total interconnect delay = 2.435 ns ( 42.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.770 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[6] Fout[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.770 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[6] Fout[6] } { 0.000ns 2.435ns } { 0.109ns 3.226ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.828 ns" { clk clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.828 ns" { clk clk~combout clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[6] } { 0.000ns 0.000ns 0.143ns 0.770ns } { 0.000ns 1.100ns 0.000ns 0.815ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.770 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[6] Fout[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.770 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[6] Fout[6] } { 0.000ns 2.435ns } { 0.109ns 3.226ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 3.056 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 3.056 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y7_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y7_N0; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.056 ns) 3.056 ns altera_reserved_tdo 2 PIN PIN_10 0 " "Info: 2: + IC(0.000 ns) + CELL(3.056 ns) = 3.056 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.056 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.056 ns ( 100.00 % ) " "Info: Total cell delay = 3.056 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.056 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.056 ns" { altera_internal_jtag~TDO altera_reserved_tdo } { 0.000ns 0.000ns } { 0.000ns 3.056ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}