📄 dds.tan.qmsg

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💻 QMSG
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "DDS.v" "" { Text "E:/EDAFIle/DDS1/DDS.v" 8 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk memory memory Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|ram_block3a0~porta_address_reg0 Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|q_a\[0\] 163.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 163.03 MHz between source memory \"Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|ram_block3a0~porta_address_reg0\" and destination memory \"Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|q_a\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "3.067 ns 3.067 ns 6.134 ns " "Info: fmax restricted to Clock High delay (3.067 ns) plus Clock Low delay (3.067 ns) : restricted to 6.134 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.641 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.641 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|ram_block3a0~porta_address_reg0 1 MEM M4K_X23_Y5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X23_Y5; Fanout = 4; MEM Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|ram_block3a0~porta_address_reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_66f2.tdf" "" { Text "E:/EDAFIle/DDS1/db/altsyncram_66f2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.641 ns) 3.641 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|q_a\[0\] 2 MEM M4K_X23_Y5 1 " "Info: 2: + IC(0.000 ns) + CELL(3.641 ns) = 3.641 ns; Loc. = M4K_X23_Y5; Fanout = 1; MEM Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|q_a\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.641 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg0 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] } "NODE_NAME" } } { "db/altsyncram_66f2.tdf" "" { Text "E:/EDAFIle/DDS1/db/altsyncram_66f2.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.641 ns ( 100.00 % ) " "Info: Total cell delay = 3.641 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.641 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg0 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.641 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg0 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.641ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.020 ns - Smallest " "Info: - Smallest clock skew is -0.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.824 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 2.824 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "DDS.v" "" { Text "E:/EDAFIle/DDS1/DDS.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns clk~clkctrl 2 COMB CLKCTRL_G2 70 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "DDS.v" "" { Text "E:/EDAFIle/DDS1/DDS.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.766 ns) + CELL(0.815 ns) 2.824 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|q_a\[0\] 3 MEM M4K_X23_Y5 1 " "Info: 3: + IC(0.766 ns) + CELL(0.815 ns) = 2.824 ns; Loc. = M4K_X23_Y5; Fanout = 1; MEM Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|q_a\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.581 ns" { clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] } "NODE_NAME" } } { "db/altsyncram_66f2.tdf" "" { Text "E:/EDAFIle/DDS1/db/altsyncram_66f2.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.915 ns ( 67.81 % ) " "Info: Total cell delay = 1.915 ns ( 67.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.909 ns ( 32.19 % ) " "Info: Total interconnect delay = 0.909 ns ( 32.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.824 ns" { clk clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.824 ns" { clk clk~combout clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] } { 0.000ns 0.000ns 0.143ns 0.766ns } { 0.000ns 1.100ns 0.000ns 0.815ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.844 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 2.844 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "DDS.v" "" { Text "E:/EDAFIle/DDS1/DDS.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns clk~clkctrl 2 COMB CLKCTRL_G2 70 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "DDS.v" "" { Text "E:/EDAFIle/DDS1/DDS.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.766 ns) + CELL(0.835 ns) 2.844 ns Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|ram_block3a0~porta_address_reg0 3 MEM M4K_X23_Y5 4 " "Info: 3: + IC(0.766 ns) + CELL(0.835 ns) = 2.844 ns; Loc. = M4K_X23_Y5; Fanout = 4; MEM Node = 'Sin_rom:U6\|altsyncram:altsyncram_component\|altsyncram_ha91:auto_generated\|altsyncram_66f2:altsyncram1\|ram_block3a0~porta_address_reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.601 ns" { clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_66f2.tdf" "" { Text "E:/EDAFIle/DDS1/db/altsyncram_66f2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.935 ns ( 68.04 % ) " "Info: Total cell delay = 1.935 ns ( 68.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.909 ns ( 31.96 % ) " "Info: Total interconnect delay = 0.909 ns ( 31.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.844 ns" { clk clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.844 ns" { clk clk~combout clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg0 } { 0.000ns 0.000ns 0.143ns 0.766ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.824 ns" { clk clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.824 ns" { clk clk~combout clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] } { 0.000ns 0.000ns 0.143ns 0.766ns } { 0.000ns 1.100ns 0.000ns 0.815ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.844 ns" { clk clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.844 ns" { clk clk~combout clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg0 } { 0.000ns 0.000ns 0.143ns 0.766ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_66f2.tdf" "" { Text "E:/EDAFIle/DDS1/db/altsyncram_66f2.tdf" 48 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_66f2.tdf" "" { Text "E:/EDAFIle/DDS1/db/altsyncram_66f2.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.641 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg0 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.641 ns" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg0 Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.641ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.824 ns" { clk clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.824 ns" { clk clk~combout clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] } { 0.000ns 0.000ns 0.143ns 0.766ns } { 0.000ns 1.100ns 0.000ns 0.815ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.844 ns" { clk clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.844 ns" { clk clk~combout clk~clkctrl Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|ram_block3a0~porta_address_reg0 } { 0.000ns 0.000ns 0.143ns 0.766ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { Sin_rom:U6|altsyncram:altsyncram_component|altsyncram_ha91:auto_generated|altsyncram_66f2:altsyncram1|q_a[0] } { 0.000ns } { 0.109ns } } } { "db/altsyncram_66f2.tdf" "" { Text "E:/EDAFIle/DDS1/db/altsyncram_66f2.tdf" 43 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 register sld_hub:sld_hub_inst\|hub_tdo 132.8 MHz 7.53 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 132.8 MHz between source register \"sld_hub:sld_hub_inst\|jtag_debug_mode_usr1\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 7.53 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.486 ns + Longest register register " "Info: + Longest register to register delay is 3.486 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 1 REG LCFF_X20_Y5_N3 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y5_N3; Fanout = 18; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.195 ns) + CELL(0.616 ns) 1.811 ns sld_hub:sld_hub_inst\|hub_tdo~562 2 COMB LCCOMB_X19_Y6_N30 1 " "Info: 2: + IC(1.195 ns) + CELL(0.616 ns) = 1.811 ns; Loc. = LCCOMB_X19_Y6_N30; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~562'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.811 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~562 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.377 ns) + CELL(0.624 ns) 2.812 ns sld_hub:sld_hub_inst\|hub_tdo~565 3 COMB LCCOMB_X19_Y6_N10 1 " "Info: 3: + IC(0.377 ns) + CELL(0.624 ns) = 2.812 ns; Loc. = LCCOMB_X19_Y6_N10; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~565'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.001 ns" { sld_hub:sld_hub_inst|hub_tdo~562 sld_hub:sld_hub_inst|hub_tdo~565 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.364 ns) + CELL(0.202 ns) 3.378 ns sld_hub:sld_hub_inst\|hub_tdo~568 4 COMB LCCOMB_X19_Y6_N12 1 " "Info: 4: + IC(0.364 ns) + CELL(0.202 ns) = 3.378 ns; Loc. = LCCOMB_X19_Y6_N12; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~568'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.566 ns" { sld_hub:sld_hub_inst|hub_tdo~565 sld_hub:sld_hub_inst|hub_tdo~568 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.486 ns sld_hub:sld_hub_inst\|hub_tdo 5 REG LCFF_X19_Y6_N13 2 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 3.486 ns; Loc. = LCFF_X19_Y6_N13; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_hub:sld_hub_inst|hub_tdo~568 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.550 ns ( 44.46 % ) " "Info: Total cell delay = 1.550 ns ( 44.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.936 ns ( 55.54 % ) " "Info: Total interconnect delay = 1.936 ns ( 55.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.486 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~562 sld_hub:sld_hub_inst|hub_tdo~565 sld_hub:sld_hub_inst|hub_tdo~568 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.486 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~562 sld_hub:sld_hub_inst|hub_tdo~565 sld_hub:sld_hub_inst|hub_tdo~568 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.195ns 0.377ns 0.364ns 0.000ns } { 0.000ns 0.616ns 0.624ns 0.202ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.015 ns - Smallest " "Info: - Smallest clock skew is -0.015 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.295 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.295 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y7_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y7_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.811 ns) + CELL(0.000 ns) 3.811 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G1 162 " "Info: 2: + IC(3.811 ns) + CELL(0.000 ns) = 3.811 ns; Loc. = CLKCTRL_G1; Fanout = 162; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.811 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.818 ns) + CELL(0.666 ns) 5.295 ns sld_hub:sld_hub_inst\|hub_tdo 3 REG LCFF_X19_Y6_N13 2 " "Info: 3: + IC(0.818 ns) + CELL(0.666 ns) = 5.295 ns; Loc. = LCFF_X19_Y6_N13; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.484 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 12.58 % ) " "Info: Total cell delay = 0.666 ns ( 12.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.629 ns ( 87.42 % ) " "Info: Total interconnect delay = 4.629 ns ( 87.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.295 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.295 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 3.811ns 0.818ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.310 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.310 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y7_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y7_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.811 ns) + CELL(0.000 ns) 3.811 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G1 162 " "Info: 2: + IC(3.811 ns) + CELL(0.000 ns) = 3.811 ns; Loc. = CLKCTRL_G1; Fanout = 162; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.811 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.666 ns) 5.310 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 3 REG LCFF_X20_Y5_N3 18 " "Info: 3: + IC(0.833 ns) + CELL(0.666 ns) = 5.310 ns; Loc. = LCFF_X20_Y5_N3; Fanout = 18; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.499 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 12.54 % ) " "Info: Total cell delay = 0.666 ns ( 12.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.644 ns ( 87.46 % ) " "Info: Total interconnect delay = 4.644 ns ( 87.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.310 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.310 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 3.811ns 0.833ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.295 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.295 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 3.811ns 0.818ns } { 0.000ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.310 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.310 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 3.811ns 0.833ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.486 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~562 sld_hub:sld_hub_inst|hub_tdo~565 sld_hub:sld_hub_inst|hub_tdo~568 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.486 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~562 sld_hub:sld_hub_inst|hub_tdo~565 sld_hub:sld_hub_inst|hub_tdo~568 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.195ns 0.377ns 0.364ns 0.000ns } { 0.000ns 0.616ns 0.624ns 0.202ns 0.108ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.295 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.295 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 3.811ns 0.818ns } { 0.000ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.310 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.310 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 3.811ns 0.833ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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