reg32b.v

基于ＦＰＧＡ平台

module REG32B(Load,Din,Dout);
  parameter size=32;
  input Load;
  input [size-1:0]Din;
  output [size-1:0]Dout;
  reg [size-1:0]Dout;
  always@(posedge Load)
    begin
      Dout<=Din;
    end
endmodule