modulation.vhd

基于FPGA的调制

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
entity modulation is
   port(clk:	in std_logic; --系统时钟
        start:	in std_logic; --开始调制信号
        x:		in std_logic; --基带信号
        y:		out std_logic); --调制信号
end modulation;
architecture behav of modulation is
	signal q:	integer range 0 to 7; --计数器
	signal xx:	std_logic_vector(1 downto 0); --中间寄存器
	signal yy:	std_logic_vector(1 downto 0); --2 位并行码寄存器
	signal f:	std_logic_vector(3 downto 0); --载波f
	begin
		process(clk) --通过对clk 分频，得到4 种相位；并完成基带信号的串并转换
			begin
				if clk'event and clk='1' then
				if start='0' then q<=0;
				elsif q=0 then q<=1;f(3)<='1'; f(1)<='0'; xx(1)<=x;yy<=xx;
				elsif q=2 then q<=3;f(2)<='0'; f(0)<='1';
				elsif q=4 then q<=5;f(3)<='0'; f(1)<='1'; xx(0)<=x;
				elsif q=6 then q<=7;f(2)<='1'; f(0)<='0';
				else q<=q+1;
				end if;
				end if;
		end process;
			y<=f(0) when yy="11" else
			f(1) when yy="10" else
			f(2) when yy="01" else
			f(3); --根据yy 寄存器数据，输出对应的载波
end behav;