nco_ip_design.map.rpt

NCO的VHDL程序

+------------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path   ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                                                     ;
+------------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------------------------------------------+
; ../nco_ip_design.mdl               ; yes             ; User File                    ; D:/eda_design/altera_design/dspbuilder_design/NCO_ip/nco_ip_design.mdl                                           ;
; db/nco_ip_design_GN8343.vhd        ; yes             ; Auto-Generated Megafunction  ; D:/eda_design/altera_design/dspbuilder_design/NCO_ip/nco_ip_design_dspbuilder/db/nco_ip_design_GN8343.vhd        ;
; db/alt_dspbuilder_clock_GN7862.vhd ; yes             ; Auto-Generated Megafunction  ; D:/eda_design/altera_design/dspbuilder_design/NCO_ip/nco_ip_design_dspbuilder/db/alt_dspbuilder_clock_GN7862.vhd ;
+------------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 0     ;
;     -- Combinational with no register       ; 0     ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 0     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 0     ;
;     -- 2 input functions                    ; 0     ;
;     -- 1 input functions                    ; 0     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 0     ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 0     ;
; I/O pins                                    ; 2     ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |nco_ip_design             ; 0 (0)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 2    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |nco_ip_design      ;              ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Copyright (C) 1991-2007 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to the 
    Info: applicable agreement for further details.
    Info: Processing started: Wed Jun 06 12:00:41 2007
Info: Command: quartus_map nco_ip_design
Warning: IP Generator Warning: internal error: in creating an instance of ICatalogCard from class com.altera.megacore.rio.AlteraRioClass in c:\altera\71\ip\rapidio\lib\ip_toolbench\rapidio.jar java.lang.NoClassDefFoundError: com/altera/sopcmodel/util/Version
Warning: IP Generator Warning: internal error: in initializing ICatalogCardProvider com.altera.megacore.pci.AlteraPCICompilerCatalogCardProvider com/altera/sopcmodel/util/Version
Warning: IP Generator Warning: internal error: in creating an instance of ICatalogCard from class com.altera.megacore.pcie.AlteraPCIECompilerClass in c:\altera\71\ip\pci_express_compiler\lib\ip_toolbench\pci_express_compiler.jar java.lang.NoClassDefFoundError: com/altera/sopcmodel/util/Version
Warning: IP Generator Warning: internal error: in initializing ICatalogCardProvider com.altera.megacore.tse.AlteraTripleSpeedEthernetCatalogCardProvider com/altera/sopcmodel/util/Version
Warning: IP Generator Warning: internal error: in creating an instance of ICatalogCard from class com.altera.nios2.AlteraNios2Class in c:\altera\71\quartus\sopc_builder\model\lib\com.altera.nios2.jar java.lang.NoClassDefFoundError: com/altera/ui/app/IEditorExtension
Info: IP Generator Info: Can't read jar file "c:\altera\71\quartus\sopc_builder\model\lib\jacl.jar"
Info: IP Generator Info: Can't read jar file "c:\altera\71\quartus\sopc_builder\model\lib\tcljava.jar"
Info: Found 2 design units, including 2 entities, in source file ../nco_ip_design.mdl
    Info: Found entity 1: nco_ip_design
    Info: Found entity 2: nco_ip_design_Interface
Info: Found 1 design units, including 1 entities, in source file ../DSPBuilder_nco_ip_design_import/nco_v7_1_st.v
    Info: Found entity 1: nco_v7_1_st
Info: Found 2 design units, including 1 entities, in source file ../DSPBuilder_nco_ip_design_import/nco_v7_1.vhd
    Info: Found design unit 1: nco_v7_1-SYN
    Info: Found entity 1: nco_v7_1
Info: Elaborating entity "nco_ip_design" for the top level hierarchy
Info: Found 2 design units, including 1 entities, in source file db/nco_ip_design_GN8343.vhd
    Info: Found design unit 1: nco_ip_design_GN8343-rtl
    Info: Found entity 1: nco_ip_design_GN8343
Info: Elaborating entity "nco_ip_design_GN8343" for hierarchy "nco_ip_design_GN8343:auto_inst"
Info: Found 2 design units, including 1 entities, in source file db/alt_dspbuilder_clock_GN7862.vhd
    Info: Found design unit 1: alt_dspbuilder_clock_GN7862-rtl
    Info: Found entity 1: alt_dspbuilder_clock_GN7862
Info: Elaborating entity "alt_dspbuilder_clock_GN7862" for hierarchy "nco_ip_design_GN8343:auto_inst|alt_dspbuilder_clock_GN7862:Clock_0"
Warning: Design contains 2 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "Clock"
    Warning: No output dependent on input pin "aclr"
Info: Implemented 2 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 0 output pins
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
    Info: Allocated 813 megabytes of memory during processing
    Info: Processing ended: Wed Jun 06 12:00:50 2007
    Info: Elapsed time: 00:00:09