alt_dspbuilder_clock.jvgen_cache.xml

NCO的VHDL程序

<?xml version="1.0" encoding="UTF-8"?>
<jvgen name="alt_dspbuilder_clock">
<instance decorated-name="alt_dspbuilder_clock_GN7862" version="7.1 Build 156 04/30/2007">
<generic name="RESET" value="ACTIVE_LOW"/>
<generic name="DOMAIN" value="default"/>
<port dir="Output" name="aclr_out" vhdl-type="std_logic"/>
<port dir="Input" name="clock" vhdl-type="std_logic"/>
<port dir="Output" name="clock_out" vhdl-type="std_logic"/>
<port dir="Input" name="aclr_n" vhdl-type="std_logic"/>
</instance>
</jvgen>