nco_ip_design.qsf

NCO的VHDL程序

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		nco_ip_design_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE AUTO
set_global_assignment -name FAMILY Stratix
set_global_assignment -name TOP_LEVEL_ENTITY nco_ip_design
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:57:45  JUNE 06, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION "6.0 SP1"
set_global_assignment -name SOURCE_FILE ../nco_ip_design.mdl
set_global_assignment -name USER_LIBRARIES "C:/altera/71/ip/nco/lib;../DSPBuilder_nco_ip_design_import/;..;../DSPBuilder_nco_ip_design_import/;..;../DSPBuilder_nco_ip_design_import/;..;"
set_global_assignment -name VERILOG_FILE "D:/eda_design/altera_design/dspbuilder_design/NCO_ip/DSPBuilder_nco_ip_design_import/nco_v7_1_st.v"
set_global_assignment -name VHDL_FILE "D:/eda_design/altera_design/dspbuilder_design/NCO_ip/DSPBuilder_nco_ip_design_import/nco_v7_1.vhd"
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name FMAX_REQUIREMENT "20 ns" -section_id Clock
set_instance_assignment -name CLOCK_SETTINGS Clock -to Clock