nco_v7_1_tb.v

NCO的VHDL程序

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//	support information, device programming or simulation file, and any other
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//   NCO COMPILER ver 6.1 VERILOG HDL TESTBENCH
`timescale 1ns / 100ps
module nco_v7_1_tb;
wire [9:0] sin_val;
reg [31:0] phi;
wire out_valid;
reg reset_n;
wire reset; 
assign reset = !reset_n;
reg clken;
reg clk;

initial
  begin
    $dumpvars;
    #0 clk = 1'b0;
    #0 reset_n = 1'b0;
    #0 clken = 1'b1;
    #0 phi = 32'b00000010100011110101110000101001;
    #69 reset_n = 1'b1;
  end

always
  begin
    #5 clk = 1;
    #5 clk = 0;
  end

integer sin_ch, sin_print;
initial
  begin
    sin_ch = $fopen ("fsin_o_ver_nco_v7_1.txt");
  end

always @(posedge clk)
  begin
    if(reset_n==1'b1 & out_valid==1'b1)
      begin
        if (sin_val[9:0] < (1<<9))
          sin_print = sin_val[9:0];
        else
          sin_print =  sin_val[9:0] - (1<<10);

    $fdisplay (sin_ch, "%d", sin_print);
      end
end

nco_v7_1 i_nco_v7_1 (
    .out_valid(out_valid),
    .fsin_o(sin_val[9:0]),
    .phi_inc_i(phi[31:0]),
    .reset_n(reset_n),
    .clken(clken),
    .clk(clk)
    );

endmodule