nco_d.txt

NCO的VHDL程序

Reading THROUGHPUT = 1
Reading CORDIC_TYPE = PARALLEL
Reading CORDIC_PIPE = 2
Reading WANT_FMOD = NO
Reading WANT_PMOD = NO
Reading PMOD_PIPELINE = 1
Reading FMOD_PIPELINE = 1
Reading WANT_DITHER = YES
Reading WANT_VLOG_SIM = YES
Reading WANT_VHDL_SIM = YES
Reading WANT_MATLAB = YES
Reading WANT_VEC = YES
Reading MPR = 10
Reading APR = 32
Reading APRF = 32
Reading APRI = 10
Reading DPRI = 5
Reading APRP = 16
Reading RDW = 10
Reading RAW = 16
Reading RAWC = 5
Reading RNWC = 32
Reading RAWF = 5
Reading RNWF = 32
Reading NUMCH = 1
Reading ACCUM_SCLR = 0
Reading MAX = 256
Reading MAXC = 320
Reading MAXF = 320
Reading PHI_INC = 42949673
Writing Trig Netlist CycloneII	Multipliers : DEDICATED
Reading RSHC = nco_v7_1_sin_c.hex
Reading RSHF = nco_v7_1_sin_f.hex
Reading RCHC = nco_v7_1_cos_c.hex
Reading RCHF = nco_v7_1_cos_f.hex
Reading MODULE_NAME = nco_v7_1_st
Reading MODULE_NAME = nco_v7_1_st
nco_v7_1_st
Reading MODULE_NAME = nco_v7_1_st
Reading CK_VALUE = 10
Reading CK_UNIT = ns
Reading NUMCH = 1
Reading ACCUM_SCLR = 0
Reading PHI_INC = 42949673
Reading MPR = 10
Reading PHI_INC = 42949673
Reading DUAL_NOT_SGL_OP = WANT_SIN_ONLY
Reading MODULE_NAME = nco_v7_1_st
Reading CK_VALUE = 10
Reading CK_UNIT = ns
Reading NUMCH = 1
Reading ACCUM_SCLR = 0
Reading PHI_INC = 42949673
Reading TARGET = CycloneII
Reading NUMCH = 1
Reading ARCH = TRIG_ARCH
Reading WANT_PMOD = NO
Reading WANT_FMOD = NO
Reading WANT_DITHER = YES
Reading MULT_TYPE = DEDICATED
Reading CORDIC_TYPE = PARALLEL
Reading CORDIC_PIPE = 2
Reading DUAL_NOT_SGL_OP = WANT_SIN_ONLY
Reading THROUGHPUT = 1
Reading MPR = 10
Reading APR = 32
Reading APRI = 10
Reading DPRI = 5
Reading APRP = 16
Reading FMOD_PIPELINE = 1
Reading APRF = 32
Reading PMOD_PIPELINE = 1
Reading WANT_DITHER = YES
Reading WANT_FMOD = NO
Reading WANT_PMOD = NO
Reading MPR = 10
Reading APRI = 10
Reading APR = 32
Reading APRP = 16
Reading APRF = 32
Reading DPRI = 5
Writing NUM_LCELLS = 256
Reading MPR = 10
Reading APRI = 10
Reading TARGET = CycloneII
Reading TARGET = CycloneII
Writing NUM_MEM_BITS = 960
Writing NUM_EABS = 1
Writing NUM_DSP_BLOCKS = 4
MSG FM-4: Found entry for SpecialPluginFrameInterface as altera.ipbu.flowmanager.defaultpack.SpecialPluginFrame creating object...
NCO 7.1
Date Stamp: Wed Jun 06 11:56:47 CST 2007
Entity Name: nco_v7_1_st	Vendor: Altera Corporation
Variation Name: nco_v7_1	Variation Language: VHDL
Working Directory: D:\eda_design\altera_design\dspbuilder_design\NCO_ip\DSPBuilder_nco_ip_design_import
MSG NF-1 Added project file "nco_v7_1_st.v" Location = 2
------------------------------------------------------------------------------------
Debug Print (wizdir =C:\altera\71\ip\nco\lib\ip_toolbench)
Debug Print (var =nco_v7_1)
Debug Print (TempDirName =D:\eda_design\altera_design\dspbuilder_design\NCO_ip\DSPBuilder_nco_ip_design_import\iptb_debug\iptb_nco_temp5099)
Debug Print (OutputDirName =D:\eda_design\altera_design\dspbuilder_design\NCO_ip\DSPBuilder_nco_ip_design_import)
Debug Print (quartusrootdir =c:\altera\71\quartus)
Debug Print (module =nco_v7_1_st)
Generating MegaCore function top-level...
MSG NF-1 Added project file "nco_v7_1.vhd" Location = 2
nco_v7_1.cmp : A VHDL component declaration for the MegaCore function variation.  Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.
MSG FM-21: runThreadedSystemCommand has executed command c:\altera\71\quartus/bin/quartus_map --generate_symbol="D:\eda_design\altera_design\dspbuilder_design\NCO_ip\DSPBuilder_nco_ip_design_import\iptb_debug\iptb_nco_temp5099\nco_v7_1.vhd" D:\eda_design\altera_design\dspbuilder_design\NCO_ip\DSPBuilder_nco_ip_design_import\iptb_debug\iptb_nco_temp5099\symbol\tempproject.qsf
MSG FM-16: runThreadedSystemCommand method is about to return exit code 0
nco_v7_1.bsf : Quartus<small><sup>&reg</sup></small> II symbol file for the MegaCore function variation.  You can use this file in the Quartus  II block diagram editor.
MSG FM-17: MonitorProgress thread is about to die
MSG SG-1: Generating Simgen Model 
Generating DSP Builder Model ...
MSG BRT-2: Adding Verilog file nco_v7_1_st.v
MSG BRT-1: Adding VHDL file nco_v7_1.vhd
Info: *******************************************************************
Info: Running Quartus II Shell
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Copyright (C) 1991-2007 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer 
to the 
    Info: applicable agreement for further details.
    Info: Processing started: Wed Jun 06 11:56:51 2007
Info: Command: quartus_sh -t quartus_simgen.tcl
Info: Evaluation of Tcl script quartus_simgen.tcl was successful
Info: Quartus II Shell was successful. 0 errors, 0 warnings
    Info: Allocated 44 megabytes of memory during processing
    Info: Processing ended: Wed Jun 06 11:56:52 2007
    Info: Elapsed time: 00:00:01
MSG FM-20: runSystemCommand method is about to return exit code 0
MSG FM-21: runThreadedSystemCommand has executed command c:\altera\71\quartus/bin/quartus_map nco_v7_1 --simgen --simgen_parameter="SIMGEN_C_NETLIST=ON,SIMGEN_OPTIMIZATION=ALL" 
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Copyright (C) 1991-2007 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.
  Please refer to the 
    Info: applicable agreement for further details.
    Info: Processing started: Wed Jun 06 11:56:55 2007
Info: Command: quartus_map nco_v7_1 --simgen --simgen_parameter=SIMGEN_C_NETLIST=ON,SIMGEN_OPTIMIZATION=ALL
Info: Found 1 design units, including 1 entities, in source file ../nco_v7_1_st.v
    Info: Found entity 1: nco_v7_1_st
Info: Found 2 design units, including 1 entities, in source file ../nco_v7_1.vhd
    Info: Found design unit 1: nco_v7_1-SYN
    Info: Found entity 1: nco_v7_1
Info: Elaborating entity "nco_v7_1" for the top level hierarchy
Info: Elaborating entity "nco_v7_1_st" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst"
Warning (10036): Verilog HDL or VHDL warning at nco_v7_1_st.v(88): object "select_s" assigned a value but never read
Warning: Using design file C:/altera/71/ip/nco/lib/asj_altqmcpipe.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1
: asj_altqmcpipe
Info: Elaborating entity "asj_altqmcpipe" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|asj_altqmcpipe:ux000"
Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborating entity "lpm_add_sub" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc"
Info: Elaborated megafunction instantiation "nco_v7_1_st:nco_v7_1_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc"
Warning: Using design file C:/altera/71/ip/nco/lib/asj_dxx_g.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: asj_dxx_g
Info: Elaborating entity "asj_dxx_g" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|asj_dxx_g:ux001"
Warning: Using design file C:/altera/71/ip/nco/lib/asj_dxx.v, which is not specified as a design file for the current project, but contains definitions for 1 de
sign units and 1 entities in project
    Info: Found entity 1: asj_dxx
Info: Elaborating entity "asj_dxx" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|asj_dxx:ux002"
Info: Elaborating entity "lpm_add_sub" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|asj_dxx:ux002|lpm_add_sub:ux014"
Info: Elaborated megafunction instantiation "nco_v7_1_st:nco_v7_1_st_inst|asj_dxx:ux002|lpm_add_sub:ux014"
Warning: Using design file C:/altera/71/ip/nco/lib/asj_nco_apr_dxx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: asj_nco_apr_dxx
Info: Elaborating entity "asj_nco_apr_dxx" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|asj_nco_apr_dxx:ux0219"
Warning: Using design file C:/altera/71/ip/nco/lib/asj_gam_dp.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: asj_gam_dp
Info: Elaborating entity "asj_g
am_dp" for hierarchy "nco_v7_1_st:nco_v7_1_st_
inst|asj_gam_dp:ux008"
Warning: Using design file C:/altera/71/ip/nco/lib/asj_nco_as_m_dp_cen.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: asj_nco_as_m_dp_cen
Info: Elaborating entity "asj_nco_as_m_dp_cen" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|asj_nco_as_m_dp_cen:ux0220"
Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "nco_v7_1_st:nco_v7_1_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component"
Warning: Using design file C:/altera/71/ip/nco/lib/asj_nco_as_m_cen.v, which is not specified as a design file for the current project, but contains definitions for 1 design units a
nd 1 entities in project
    Info: Found entity 1: asj_nco_as_m_cen
Info: Elaborating entity "asj_nco_as_m_cen" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|asj_nco_as_m_cen:ux0122"
Info: Elaborating entity "altsyncram" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0"
Info: Elaborated megafunction instantiation "nco_v7_1_st:nco_v7_1_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0"
Info: Elaborating entity "asj_nco_as_m_cen" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|asj_nco_as_m_cen:ux0123"
Info: Elaborating entity "altsyncram" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0"
Info: Elaborated megafunction instantiation "nco_v7_1_st:nco_v7_1_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0"
Warning: Using design file C:/altera/71/ip/nco/lib/mac_i_lpmd.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 
1 entities in project
    Info: Found entity 1: mac_i_lpmd
Info: Elaborating entity "mac_i_lpmd" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|mac_i_lpmd:m0"
Warning: Using design file C:/altera/71/ip/nco/lib/lmsd.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lmsd
Info: Elaborating entity "lmsd" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|mac_i_lpmd:m0|lmsd:m_0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/lpm_mult.tdf
    Info: Found entity 1: lpm_mult
Info: Elaborating entity "lpm_mult" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component"
Info: Elaborated megafunction instantiation "nco_v7_1_st:nco_v7_1_st_inst|mac_i_lpmd:m0|lmsd:m_0|lpm_mult:lpm_mult_component"
Warning: Using design file C:/altera/71/ip/nco/lib/las.v, which is not specified as a design file for the current pro
ject, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: las
Info: Elaborating entity "las" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|mac_i_lpmd:m0|las:a_0"
Info: Elaborating entity "lpm_add_sub" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|mac_i_lpmd:m0|las:a_0|lpm_add_sub:lpm_add_sub_component"
Info: Elaborated megafunction instantiation "nco_v7_1_st:nco_v7_1_st_inst|mac_i_lpmd:m0|las:a_0|lpm_add_sub:lpm_add_sub_component"
Warning: Using design file C:/altera/71/ip/nco/lib/asj_nco_derot.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: asj_nco_derot
Info: Elaborating entity "asj_nco_derot" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|asj_nco_derot:ux0136"
Warning: Using design file C:/altera/71/ip/nco/lib/asj_nco_mob_w.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities
 in project
    Info: Found entity
 1: asj_nco_mob_w
Info: Elaborating entity "asj_nco_mob_w" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|asj_nco_mob_w:blk0"
Info: Elaborating entity "lpm_add_sub" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component"
Info: Elaborated megafunction instantiation "nco_v7_1_st:nco_v7_1_st_inst|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component"
Warning: Using design file C:/altera/71/ip/nco/lib/asj_nco_isdr.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: asj_nco_isdr
Info: Elaborating entity "asj_nco_isdr" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|asj_nco_isdr:ux710isdr"
Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborating entity "lpm_counter" for hierarchy "nco_v7_1_st:nco_v7_1_st_inst|asj_nco_isdr:ux710isdr|lpm_coun
ter:lpm_counter_component"
Info: Elaborated megafunction instantiation "nco_v7_1_st:nco_v7_1_st_inst|asj_nco_isdr:ux710isdr|lpm_counter:lpm_counter_component"
Warning: Port "datab" on the entity instantiation of "lpm_add_sub_component" is connected to a signal of width 32. The formal width of the signal in the module is 10.  Extra bits will be ignored.
Warning: Port "data_in" on the entity instantiation of "blk0" is connected to a signal of width 21. The formal width of the signal in the module is 20.  Extra bits will be ignored.
Warning: Port "pcc_d" on the entity instantiation of "ux0219" is connected to a signal of width 15. The formal width of the signal in the module is 16.  Extra bits will be left dangling without any fanout logic.
Info: Generating sgate simulator netlist using Simgen
SIMGEN_PROGRESS Start of Model generation -- 0% complete
SIMGEN_PROGRESS Phase 1 : Internal Objects created -- 25% complete
SIMGEN_PROGRESS Phase 2 : Connections between internal objects made -- 60% complete
SIMGEN_PROGRESS Phase 3 : Netlist generated -- 100% complete
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 17 warnings
    Info: Allocated 198 megabytes of memory during processing
    Info: Processing ended: Wed Jun 06 11:57:02 2007
    Info: Elapsed time: 00:00:07
MSG FM-16: runThreadedSystemCommand method is about to return exit code 0
nco_v7_1.vo : Simulation Model
MSG FM-17: MonitorProgress thread is about to die
MSG APF-2: Adding Project Files
Adding Design Files to Quartus project ...
MSG APF-6: Processing nco_v7_1_st.v
MSG BRT-2: Adding Verilog file nco_v7_1_st.v
MSG APF-6: Processing nco_v7_1.vhd
MSG BRT-1: Adding VHDL file nco_v7_1.vhd
MSG APF-8: Processing nco_v7_1_st.v
MSG APF-1: Adding Tcl file nco_v7_1_st.v
MSG APF-1: Adding Tcl file nco_v7_1_st.v
MSG APF-8: Processing nco_v7_1.vhd
MSG APF-1: Adding Tcl file nco_v7_1.vhd
MSG APF-1: Adding Tcl file nco_v7_1.vhd
MSG APF-10: Copying Tcl script to DSP Builder temp directory.
MSG APF-2: Adding Project Files
Adding Design Files to Quartus project ...
MSG APF-6: Processing nco_v7_1_st.v
MSG BRT-2: Adding Verilog file nco_v7_1_st.v
MSG APF-6: Processing nco_v7_1.vhd
MSG BRT-1: Adding VHDL file nco_v7_1.vhd
MSG APF-8: Processing nco_v7_1_st.v
MSG APF-1: Adding Tcl file nco_v7_1_st.v
MSG APF-1: Adding Tcl file nco_v7_1_st.v
MSG APF-8: Processing nco_v7_1.vhd
MSG APF-1: Adding Tcl file nco_v7_1.vhd
MSG APF-1: Adding Tcl file nco_v7_1.vhd
MSG APF-10: Copying Tcl script to DSP Builder temp directory.
MegaCore Function Generation Successful.
MSG FMP-1: Posting close event for IP Toolbench. Application will exit now.
MSG FM-7: Calling uninitialize on FlowManager
MSG SFP-3: Worker thread: 1810371957 is now dead
MSG FM-11: Flowmanager Event Dispatcher -1384083551 is interrupted by framework
MSG FM-9: Flowmanager Event Dispatcher -1384083551 is now dead
MSG FM-11: Task dispatcher thread -1271396648 is interrupted by framework
MSG DTL-1: Task dispatcher thread -1271396648 is now dead