generate_test_netlist.txt

来自「NCO的VHDL程序」· 文本 代码 · 共 9 行

D:\eda_design\altera_design\dspbuilder_design\NCO_ip>set QESS_ROOTDIR=c:\altera\71\quartus 

D:\eda_design\altera_design\dspbuilder_design\NCO_ip>set QUARTUS_ROOTDIR=c:\altera\71\quartus 

D:\eda_design\altera_design\dspbuilder_design\NCO_ip>cd D:\eda_design\altera_design\dspbuilder_design\NCO_ip\DSPBuilder_nco_ip_design_import 

D:\eda_design\altera_design\dspbuilder_design\NCO_ip\DSPBuilder_nco_ip_design_import>"C:\altera\71\ip\nco\lib\..\..\common\ip_toolbench\v1.3.0\bin\ip_toolbench.exe"  -simgen_enable.language:vhdl -simgen_enable.enabled:1 -silent -flow_dir:c:\altera\71\quartus\common\ip -alt_flow_dir:C:\altera\71\ip\nco\lib\..\..\common\ip_toolbench\v1.3.0\bin -devicefamily:"Stratix" -core_dir:C:\altera\71\ip\nco\lib\ip_toolbench -wizard:nco "D:\eda_design\altera_design\dspbuilder_design\NCO_ip\DSPBuilder_nco_ip_design_import\nco_v7_1.vhd"