nco_ip_design.mdl

NCO的VHDL程序

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      vofile		      "DSPBuilder_nco_ip_design_import\\nco_v7_1.vo"
      n_input_port	      "3"
      n_output_port	      "2"
      core_dir		      "C:\\altera\\71\\ip\\nco\\lib\\ip_toolbench"
      core_name		      "nco"
      clockname		      "clk"
      flow_dir		      "C:\\altera\\71\\ip\\nco\\lib\\../../common/ip_t"
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      VhdlVariationDate	      "06-Jun-2007 11:57:03"
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