nco_ip_design.mdlxml

NCO的VHDL程序

<?xml version="1.0" encoding="UTF-8"?>
<model fullName="nco_ip_design" name="nco_ip_design" subtype="Subsystem" synthesizable="true" type="SubSystem" checksum="3356359150" modelLocation="D:\eda_design\altera_design\dspbuilder_design\NCO_ip\nco_ip_design.mdl" modelDate="2007-06-06"><clockdomain export="false" name="Clock" InitialClockValue="1" Period="20 ns" PhaseDelay="0 fs" SimulationStartCycle="5" Reset="aclr" ResetType="ACTIVE_LOW"/><block><simulinkBlock fullName="nco_ip_design/Signal Compiler" name="Signal_Compiler" subtype="S-Function" synthesizable="false" type="SimulinkBlock"><generic name="UseBoardBlock" value="off"/><generic name="EnableSignalTap" value="off"/><generic name="SignalTapDepth" value="128"/><generic name="StpUseDefaultClock" value="on"/><generic name="DeviceName" value="AUTO"/><generic name="DeviceFamily" value="Stratix"/><generic name="StpClock" value="Clock"/></simulinkBlock></block><block><libraryBlock fullName="nco_ip_design/nco_v7_1" name="nco_v7_1" subtype="com.altera.dspbuilder.blockset.megacorefunctions.MegaCore" synthesizable="true" type="LibraryBlock" entityName="nco_v7_1_import"><connectionPoint name="clken" index="0" clockdomain="Clock" bwl="1" bwr="0" dataType="bit" direction="input" type="wire" implicit="none"/><connectionPoint name="phi_inc_i" index="1" clockdomain="Clock" bwl="32" bwr="0" dataType="uint" direction="input" type="wire" implicit="none"/><connectionPoint name="reset_n" index="2" clockdomain="Clock" bwl="1" bwr="0" dataType="bit" direction="input" type="wire" implicit="none"/><connectionPoint name="fsin_o" index="0" clockdomain="Clock" bwl="10" bwr="0" dataType="int" direction="output" type="wire" implicit="none"/><connectionPoint name="out_valid" index="1" clockdomain="Clock" bwl="1" bwr="0" dataType="bit" direction="output" type="wire" implicit="none"/></libraryBlock></block><version numbers="7 1 156" longstring="7.1 Build 156 04/30/2007" shortstring="7.1" date="2007-06-06"/></model>