uart.fit.eqn

串口程序

--state_rec[0] is state_rec[0] at LC_X12_Y13_N9
--operation mode is normal

state_rec[0]_lut_out = A1L240 & (state_rec[0]) # !A1L240 & (A1L241 & state_rec[0] # !A1L241 & !state_rec[0] & !A1L246);
state_rec[0] = DFFEAS(state_rec[0]_lut_out, GLOBAL(clkbaud8x), GLOBAL(rst), , , , , , );


--state_rec[3] is state_rec[3] at LC_X13_Y13_N9
--operation mode is normal

state_rec[3]_lut_out = A1L242 & state_rec[3] # !A1L242 & !A1L246 & (state_rec[3] $ A1L2);
state_rec[3] = DFFEAS(state_rec[3]_lut_out, GLOBAL(clkbaud8x), GLOBAL(rst), , , , , , );


--A1L211 is rxd_buf[7]~168 at LC_X13_Y13_N7
--operation mode is normal

A1L211 = A1L210 & (state_rec[3] $ (state_rec[0] # !A1L193));


--key_entry1 is key_entry1 at LC_X21_Y6_N5
--operation mode is normal

key_entry1_lut_out = key_entry1 # !key_input & !A1L192;
key_entry1 = DFFEAS(key_entry1_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , key_entry2, );


--A1L294 is txd_reg~747 at LC_X25_Y6_N8
--operation mode is normal

A1L294 = div8_tras_reg[0] & div8_tras_reg[1] & div8_tras_reg[2];


--A1L184 is Mux~6940 at LC_X24_Y7_N4
--operation mode is normal

A1L184 = state_tras[0] & state_tras[1];


--A1L228 is send_state[2]~284 at LC_X23_Y6_N9
--operation mode is normal

A1L228 = state_tras[2] & state_tras[3];


--A1L229 is send_state[2]~285 at LC_X23_Y6_N5
--operation mode is normal

A1L229 = A1L228 & key_entry2 & state_tras[1] & state_tras[0];


--A1L226 is send_state[1]~287 at LC_X25_Y6_N6
--operation mode is normal

A1L226 = A1L229 & A1L294 & send_state[0];


--A1L185 is Mux~6944 at LC_X22_Y6_N3
--operation mode is normal

A1L185 = state_tras[3] & !state_tras[2] & (!state_tras[1]) # !state_tras[3] & (state_tras[2] # state_tras[0] # state_tras[1]);


--A1L253 is trasstart~710 at LC_X22_Y6_N4
--operation mode is normal

A1L253 = key_entry2 & !A1L185;


--A1L254 is trasstart~711 at LC_X24_Y6_N8
--operation mode is normal

A1L254 = state_tras[3] & (state_tras[2] & (!state_tras[0] # !state_tras[1]) # !state_tras[2] & state_tras[1]);


--A1L255 is trasstart~712 at LC_X22_Y6_N2
--operation mode is normal

A1L255 = A1L294 & (A1L254 # !A1L289 & A1L260) # !A1L294 & !A1L289 & A1L260;


--A1L271 is txd_buf~1833 at LC_X23_Y6_N1
--operation mode is normal

A1L271 = state_tras[3] & (state_tras[1]);


--A1L272 is txd_buf~1834 at LC_X23_Y6_N8
--operation mode is normal

A1L272 = A1L271 & (send_state[2] & (!send_state[1]) # !send_state[2] & (send_state[1] # !send_state[0]));


--txd_buf[1] is txd_buf[1] at LC_X23_Y7_N9
--operation mode is normal

txd_buf[1]_lut_out = A1L265 & txd_buf[2] # !A1L265 & (A1L274);
txd_buf[1] = DFFEAS(txd_buf[1]_lut_out, GLOBAL(clkbaud8x), GLOBAL(rst), , A1L262, VCC, , , !key_entry2);


--A1L273 is txd_buf~1835 at LC_X24_Y7_N9
--operation mode is normal

A1L273 = txd_buf[1] & (!state_tras[3] # !state_tras[1]) # !key_entry2;


--A1L261 is txd_buf[0]~1836 at LC_X23_Y6_N2
--operation mode is normal

A1L261 = state_tras[2] # !state_tras[3] # !state_tras[0];


--A1L262 is txd_buf[0]~1838 at LC_X24_Y6_N6
--operation mode is normal

A1L262 = key_entry2 & (!A1L260 & !A1L263) # !key_entry2 & key_entry1;


--div_reg[14] is div_reg[14] at LC_X20_Y12_N8
--operation mode is normal

div_reg[14]_lut_out = A1L4;
div_reg[14] = DFFEAS(div_reg[14]_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--div_reg[13] is div_reg[13] at LC_X22_Y12_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

div_reg[13]_lut_out = GND;
div_reg[13] = DFFEAS(div_reg[13]_lut_out, GLOBAL(clk), GLOBAL(rst), , , A1L7, , , VCC);


--div_reg[12] is div_reg[12] at LC_X21_Y12_N2
--operation mode is normal

div_reg[12]_lut_out = A1L10;
div_reg[12] = DFFEAS(div_reg[12]_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--A1L194 is rtl~240 at LC_X20_Y12_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

div_reg[15]_qfbk = div_reg[15];
A1L194 = !div_reg[12] & !div_reg[14] & !div_reg[15]_qfbk & !div_reg[13];

--div_reg[15] is div_reg[15] at LC_X20_Y12_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

div_reg[15] = DFFEAS(A1L194, GLOBAL(clk), GLOBAL(rst), , , A1L3, , , VCC);


--div_reg[8] is div_reg[8] at LC_X20_Y11_N7
--operation mode is normal

div_reg[8]_lut_out = !A1L198 & (A1L12);
div_reg[8] = DFFEAS(div_reg[8]_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--div_reg[10] is div_reg[10] at LC_X20_Y11_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

div_reg[10]_lut_out = GND;
div_reg[10] = DFFEAS(div_reg[10]_lut_out, GLOBAL(clk), GLOBAL(rst), , , A1L18, , , VCC);


--div_reg[9] is div_reg[9] at LC_X20_Y11_N1
--operation mode is normal

div_reg[9]_lut_out = A1L21;
div_reg[9] = DFFEAS(div_reg[9]_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--A1L195 is rtl~241 at LC_X20_Y11_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

div_reg[11]_qfbk = div_reg[11];
A1L195 = div_reg[8] & !div_reg[10] & !div_reg[11]_qfbk & !div_reg[9];

--div_reg[11] is div_reg[11] at LC_X20_Y11_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

div_reg[11] = DFFEAS(A1L195, GLOBAL(clk), GLOBAL(rst), , , A1L15, , , VCC);


--div_reg[6] is div_reg[6] at LC_X19_Y12_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

div_reg[6]_lut_out = GND;
div_reg[6] = DFFEAS(div_reg[6]_lut_out, GLOBAL(clk), GLOBAL(rst), , , A1L26, , , VCC);


--div_reg[5] is div_reg[5] at LC_X20_Y11_N5
--operation mode is normal

div_reg[5]_lut_out = A1L29;
div_reg[5] = DFFEAS(div_reg[5]_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--div_reg[4] is div_reg[4] at LC_X20_Y11_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

div_reg[4]_lut_out = GND;
div_reg[4] = DFFEAS(div_reg[4]_lut_out, GLOBAL(clk), GLOBAL(rst), , , A1L32, , , VCC);


--A1L196 is rtl~242 at LC_X20_Y11_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

div_reg[7]_qfbk = div_reg[7];
A1L196 = !div_reg[6] & !div_reg[5] & !div_reg[7]_qfbk & !div_reg[4];

--div_reg[7] is div_reg[7] at LC_X20_Y11_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

div_reg[7] = DFFEAS(A1L196, GLOBAL(clk), GLOBAL(rst), , , A1L24, , , VCC);


--div_reg[0] is div_reg[0] at LC_X20_Y13_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

div_reg[0]_lut_out = GND;
div_reg[0] = DFFEAS(div_reg[0]_lut_out, GLOBAL(clk), GLOBAL(rst), , , A1L38, , , VCC);


--div_reg[3] is div_reg[3] at LC_X21_Y13_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

div_reg[3]_lut_out = GND;
div_reg[3] = DFFEAS(div_reg[3]_lut_out, GLOBAL(clk), GLOBAL(rst), , , A1L41, , , VCC);


--div_reg[2] is div_reg[2] at LC_X20_Y11_N4
--operation mode is normal

div_reg[2]_lut_out = !A1L198 & A1L44;
div_reg[2] = DFFEAS(div_reg[2]_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--A1L197 is rtl~243 at LC_X20_Y13_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

div_reg[1]_qfbk = div_reg[1];
A1L197 = !div_reg[3] & !div_reg[2] & div_reg[1]_qfbk & div_reg[0];

--div_reg[1] is div_reg[1] at LC_X20_Y13_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

div_reg[1] = DFFEAS(A1L197, GLOBAL(clk), GLOBAL(rst), , , A1L35, , , VCC);


--A1L198 is rtl~244 at LC_X20_Y11_N3
--operation mode is normal

A1L198 = A1L196 & A1L197 & A1L195 & A1L194;


--rxd_reg1 is rxd_reg1 at LC_X23_Y15_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

rxd_reg1_lut_out = GND;
rxd_reg1 = DFFEAS(rxd_reg1_lut_out, GLOBAL(clkbaud8x), GLOBAL(rst), , , rxd, , , VCC);


--recstart is recstart at LC_X12_Y13_N5
--operation mode is normal

recstart_lut_out = A1L189 & (recstart # A1L191 & recstart_tmp) # !A1L189 & A1L191 & recstart_tmp;
recstart = DFFEAS(recstart_lut_out, GLOBAL(clkbaud8x), GLOBAL(rst), , , , , , );


--A1L240 is state_rec[0]~737 at LC_X13_Y13_N2
--operation mode is normal

A1L240 = div8_rec_reg[1] & (state_rec[3] & !A1L193) # !div8_rec_reg[1] & (state_rec[0] # state_rec[3] # !A1L193);


--A1L191 is rtl~2 at LC_X13_Y13_N4
--operation mode is normal

A1L191 = !state_rec[3] & !state_rec[0] & !state_rec[1] & !state_rec[2];


--recstart_tmp is recstart_tmp at LC_X13_Y15_N2
--operation mode is normal

recstart_tmp_lut_out = recstart_tmp & (!A1L191) # !recstart_tmp & rxd_reg2 & !rxd_reg1 & A1L191;
recstart_tmp = DFFEAS(recstart_tmp_lut_out, GLOBAL(clkbaud8x), GLOBAL(rst), , , , , , );


--A1L241 is state_rec[0]~738 at LC_X13_Y13_N5
--operation mode is normal

A1L241 = A1L191 & !recstart_tmp # !A1L191 & (!div8_rec_reg[0] # !div8_rec_reg[2]);


--A1L242 is state_rec[0]~739 at LC_X13_Y13_N3
--operation mode is normal

A1L242 = A1L240 # A1L241;


--A1L1 is add~896 at LC_X12_Y13_N4
--operation mode is normal

A1L1 = state_rec[0] & state_rec[1];


--A1L246 is state_rec~740 at LC_X12_Y13_N3
--operation mode is normal

A1L246 = state_rec[3] & (state_rec[1] # state_rec[0] # state_rec[2]);


--A1L2 is add~897 at LC_X12_Y13_N7
--operation mode is normal

A1L2 = state_rec[1] & (state_rec[0] & state_rec[2]);


--cnt_delay[19] is cnt_delay[19] at LC_X21_Y7_N8
--operation mode is normal

cnt_delay[19]_lut_out = A1L46 & A1L192;
cnt_delay[19] = DFFEAS(cnt_delay[19]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[18] is cnt_delay[18] at LC_X21_Y7_N0
--operation mode is normal

cnt_delay[18]_lut_out = A1L192 & (A1L47);
cnt_delay[18] = DFFEAS(cnt_delay[18]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[13] is cnt_delay[13] at LC_X21_Y6_N8
--operation mode is normal

cnt_delay[13]_lut_out = A1L50 & A1L192;
cnt_delay[13] = DFFEAS(cnt_delay[13]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[12] is cnt_delay[12] at LC_X21_Y7_N4
--operation mode is normal

cnt_delay[12]_lut_out = A1L192 & (A1L53);
cnt_delay[12] = DFFEAS(cnt_delay[12]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--A1L199 is rtl~245 at LC_X21_Y7_N2
--operation mode is normal

A1L199 = !cnt_delay[18] # !cnt_delay[19] # !cnt_delay[12] # !cnt_delay[13];


--cnt_delay[16] is cnt_delay[16] at LC_X21_Y6_N3
--operation mode is normal

cnt_delay[16]_lut_out = A1L59;
cnt_delay[16] = DFFEAS(cnt_delay[16]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[15] is cnt_delay[15] at LC_X19_Y7_N0
--operation mode is normal

cnt_delay[15]_lut_out = A1L62;
cnt_delay[15] = DFFEAS(cnt_delay[15]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[14] is cnt_delay[14] at LC_X19_Y7_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[14]_lut_out = GND;
cnt_delay[14] = DFFEAS(cnt_delay[14]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L65, , , VCC);


--A1L231 is start_delaycnt~221 at LC_X21_Y7_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[17]_qfbk = cnt_delay[17];
A1L231 = !cnt_delay[14] & !cnt_delay[16] & !cnt_delay[17]_qfbk & !cnt_delay[15];

--cnt_delay[17] is cnt_delay[17] at LC_X21_Y7_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[17] = DFFEAS(A1L231, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L56, , , VCC);


--cnt_delay[9] is cnt_delay[9] at LC_X19_Y7_N6
--operation mode is normal

cnt_delay[9]_lut_out = A1L70;
cnt_delay[9] = DFFEAS(cnt_delay[9]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[7] is cnt_delay[7] at LC_X19_Y7_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[7]_lut_out = GND;
cnt_delay[7] = DFFEAS(cnt_delay[7]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L72, , , VCC);


--cnt_delay[6] is cnt_delay[6] at LC_X19_Y7_N1
--operation mode is normal

cnt_delay[6]_lut_out = A1L75;
cnt_delay[6] = DFFEAS(cnt_delay[6]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--A1L232 is start_delaycnt~222 at LC_X21_Y7_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[11]_qfbk = cnt_delay[11];
A1L232 = !cnt_delay[9] & !cnt_delay[7] & !cnt_delay[11]_qfbk & !cnt_delay[6];

--cnt_delay[11] is cnt_delay[11] at LC_X21_Y7_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[11] = DFFEAS(A1L232, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L67, , , VCC);


--cnt_delay[4] is cnt_delay[4] at LC_X19_Y7_N8
--operation mode is normal

cnt_delay[4]_lut_out = A1L81;
cnt_delay[4] = DFFEAS(cnt_delay[4]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[3] is cnt_delay[3] at LC_X19_Y7_N5
--operation mode is normal

cnt_delay[3]_lut_out = A1L83;
cnt_delay[3] = DFFEAS(cnt_delay[3]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[2] is cnt_delay[2] at LC_X19_Y7_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[2]_lut_out = GND;
cnt_delay[2] = DFFEAS(cnt_delay[2]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L86, , , VCC);


--A1L233 is start_delaycnt~223 at LC_X21_Y7_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.