uartt.hier_info

串口程序

|uartt
dout <= UART:inst.txd
clk => appl:inst1.inclk0
reset => UART:inst.rst
din => UART:inst.rxd
skp => UART:inst.key_input
en <= UART:inst.en
seg_out[0] <= UART:inst.seg_data[0]
seg_out[1] <= UART:inst.seg_data[1]
seg_out[2] <= UART:inst.seg_data[2]
seg_out[3] <= UART:inst.seg_data[3]
seg_out[4] <= UART:inst.seg_data[4]
seg_out[5] <= UART:inst.seg_data[5]
seg_out[6] <= UART:inst.seg_data[6]
seg_out[7] <= UART:inst.seg_data[7]


|uartt|UART:inst
clk => clkbaud8x.CLK
clk => div_reg[0].CLK
clk => div_reg[1].CLK
clk => div_reg[2].CLK
clk => div_reg[3].CLK
clk => div_reg[4].CLK
clk => div_reg[5].CLK
clk => div_reg[6].CLK
clk => div_reg[7].CLK
clk => div_reg[8].CLK
clk => div_reg[9].CLK
clk => div_reg[10].CLK
clk => div_reg[11].CLK
clk => div_reg[12].CLK
clk => div_reg[13].CLK
clk => div_reg[14].CLK
clk => div_reg[15].CLK
clk => key_entry1.CLK
clk => start_delaycnt.CLK
clk => cnt_delay[0].CLK
clk => cnt_delay[1].CLK
clk => cnt_delay[2].CLK
clk => cnt_delay[3].CLK
clk => cnt_delay[4].CLK
clk => cnt_delay[5].CLK
clk => cnt_delay[6].CLK
clk => cnt_delay[7].CLK
clk => cnt_delay[8].CLK
clk => cnt_delay[9].CLK
clk => cnt_delay[10].CLK
clk => cnt_delay[11].CLK
clk => cnt_delay[12].CLK
clk => cnt_delay[13].CLK
clk => cnt_delay[14].CLK
clk => cnt_delay[15].CLK
clk => cnt_delay[16].CLK
clk => cnt_delay[17].CLK
clk => cnt_delay[18].CLK
clk => cnt_delay[19].CLK
rst => div8_tras_reg[2].ACLR
rst => div8_tras_reg[1].ACLR
rst => div8_tras_reg[0].ACLR
rst => rxd_reg1.ACLR
rst => rxd_reg2.ACLR
rst => rxd_buf[7].ACLR
rst => rxd_buf[6].ACLR
rst => rxd_buf[5].ACLR
rst => rxd_buf[4].ACLR
rst => rxd_buf[3].ACLR
rst => rxd_buf[2].ACLR
rst => rxd_buf[1].ACLR
rst => rxd_buf[0].ACLR
rst => state_rec[3].ACLR
rst => state_rec[2].ACLR
rst => state_rec[1].ACLR
rst => state_rec[0].ACLR
rst => recstart.ACLR
rst => key_entry2.ACLR
rst => send_state[0].ACLR
rst => send_state[1].ACLR
rst => send_state[2].ACLR
rst => state_tras[0].ACLR
rst => state_tras[1].ACLR
rst => state_tras[2].ACLR
rst => state_tras[3].ACLR
rst => txd_buf[0].ACLR
rst => txd_buf[1].ACLR
rst => txd_buf[2].ACLR
rst => txd_buf[3].ACLR
rst => txd_buf[4].ACLR
rst => txd_buf[5].ACLR
rst => txd_buf[6].ACLR
rst => txd_buf[7].ACLR
rst => trasstart.ACLR
rst => txd_reg.PRESET
rst => recstart_tmp.ACLR
rst => div8_rec_reg[0].ACLR
rst => div8_rec_reg[1].ACLR
rst => div8_rec_reg[2].ACLR
rst => clkbaud8x.ACLR
rst => div_reg[0].ACLR
rst => div_reg[1].ACLR
rst => div_reg[2].ACLR
rst => div_reg[3].ACLR
rst => div_reg[4].ACLR
rst => div_reg[5].ACLR
rst => div_reg[6].ACLR
rst => div_reg[7].ACLR
rst => div_reg[8].ACLR
rst => div_reg[9].ACLR
rst => div_reg[10].ACLR
rst => div_reg[11].ACLR
rst => div_reg[12].ACLR
rst => div_reg[13].ACLR
rst => div_reg[14].ACLR
rst => div_reg[15].ACLR
rst => key_entry1.ACLR
rst => start_delaycnt.ACLR
rst => cnt_delay[0].ACLR
rst => cnt_delay[1].ACLR
rst => cnt_delay[2].ACLR
rst => cnt_delay[3].ACLR
rst => cnt_delay[4].ACLR
rst => cnt_delay[5].ACLR
rst => cnt_delay[6].ACLR
rst => cnt_delay[7].ACLR
rst => cnt_delay[8].ACLR
rst => cnt_delay[9].ACLR
rst => cnt_delay[10].ACLR
rst => cnt_delay[11].ACLR
rst => cnt_delay[12].ACLR
rst => cnt_delay[13].ACLR
rst => cnt_delay[14].ACLR
rst => cnt_delay[15].ACLR
rst => cnt_delay[16].ACLR
rst => cnt_delay[17].ACLR
rst => cnt_delay[18].ACLR
rst => cnt_delay[19].ACLR
rxd => rxd_reg1.DATAIN
txd <= txd_reg.DB_MAX_OUTPUT_PORT_TYPE
en <= <GND>
seg_data[0] <= <VCC>
seg_data[1] <= Mux29.DB_MAX_OUTPUT_PORT_TYPE
seg_data[2] <= Mux28.DB_MAX_OUTPUT_PORT_TYPE
seg_data[3] <= Mux27.DB_MAX_OUTPUT_PORT_TYPE
seg_data[4] <= Mux26.DB_MAX_OUTPUT_PORT_TYPE
seg_data[5] <= Mux25.DB_MAX_OUTPUT_PORT_TYPE
seg_data[6] <= Mux24.DB_MAX_OUTPUT_PORT_TYPE
seg_data[7] <= Mux23.DB_MAX_OUTPUT_PORT_TYPE
key_input => key_entry1~0.OUTPUTSELECT
key_input => process0~0.IN0


|uartt|appl:inst1
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]


|uartt|appl:inst1|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= <UNC>
clk[2] <= <UNC>
clk[3] <= <UNC>
clk[4] <= <UNC>
clk[5] <= <UNC>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE