📄 uart.tan.qmsg

📁 串口程序
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register key_entry2 register key_entry1 150.81 MHz 6.631 ns Internal " "Info: Clock \"clk\" has Internal fmax of 150.81 MHz between source register \"key_entry2\" and destination register \"key_entry1\" (period= 6.631 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.925 ns + Longest register register " "Info: + Longest register to register delay is 1.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_entry2 1 REG LC_X22_Y11_N7 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y11_N7; Fanout = 19; REG Node = 'key_entry2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key_entry2 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.813 ns) + CELL(1.112 ns) 1.925 ns key_entry1 2 REG LC_X21_Y11_N0 4 " "Info: 2: + IC(0.813 ns) + CELL(1.112 ns) = 1.925 ns; Loc. = LC_X21_Y11_N0; Fanout = 4; REG Node = 'key_entry1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.925 ns" { key_entry2 key_entry1 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.112 ns ( 57.77 % ) " "Info: Total cell delay = 1.112 ns ( 57.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.813 ns ( 42.23 % ) " "Info: Total interconnect delay = 0.813 ns ( 42.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.925 ns" { key_entry2 key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.925 ns" { key_entry2 key_entry1 } { 0.000ns 0.813ns } { 0.000ns 1.112ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.445 ns - Smallest " "Info: - Smallest clock skew is -4.445 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.942 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns key_entry1 2 REG LC_X21_Y11_N0 4 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X21_Y11_N0; Fanout = 4; REG Node = 'key_entry1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.473 ns" { clk key_entry1 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 key_entry1 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.387 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.387 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clkbaud8x 2 REG LC_X8_Y10_N9 40 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N9; Fanout = 40; REG Node = 'clkbaud8x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk clkbaud8x } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.527 ns) + CELL(0.711 ns) 7.387 ns key_entry2 3 REG LC_X22_Y11_N7 19 " "Info: 3: + IC(3.527 ns) + CELL(0.711 ns) = 7.387 ns; Loc. = LC_X22_Y11_N7; Fanout = 19; REG Node = 'key_entry2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.238 ns" { clkbaud8x key_entry2 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.17 % ) " "Info: Total cell delay = 3.115 ns ( 42.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.272 ns ( 57.83 % ) " "Info: Total interconnect delay = 4.272 ns ( 57.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.387 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.387 ns" { clk clk~out0 clkbaud8x key_entry2 } { 0.000ns 0.000ns 0.745ns 3.527ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 key_entry1 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.387 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.387 ns" { clk clk~out0 clkbaud8x key_entry2 } { 0.000ns 0.000ns 0.745ns 3.527ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.925 ns" { key_entry2 key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.925 ns" { key_entry2 key_entry1 } { 0.000ns 0.813ns } { 0.000ns 1.112ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 key_entry1 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.387 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.387 ns" { clk clk~out0 clkbaud8x key_entry2 } { 0.000ns 0.000ns 0.745ns 3.527ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 7 " "Warning: Circuit may not operate. Detected 7 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "key_entry1 key_entry2 clk 3.348 ns " "Info: Found hold time violation between source  pin or register \"key_entry1\" and destination pin or register \"key_entry2\" for clock \"clk\" (Hold time is 3.348 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.445 ns + Largest " "Info: + Largest clock skew is 4.445 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.387 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.387 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clkbaud8x 2 REG LC_X8_Y10_N9 40 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N9; Fanout = 40; REG Node = 'clkbaud8x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk clkbaud8x } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.527 ns) + CELL(0.711 ns) 7.387 ns key_entry2 3 REG LC_X22_Y11_N7 19 " "Info: 3: + IC(3.527 ns) + CELL(0.711 ns) = 7.387 ns; Loc. = LC_X22_Y11_N7; Fanout = 19; REG Node = 'key_entry2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.238 ns" { clkbaud8x key_entry2 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.17 % ) " "Info: Total cell delay = 3.115 ns ( 42.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.272 ns ( 57.83 % ) " "Info: Total interconnect delay = 4.272 ns ( 57.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.387 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.387 ns" { clk clk~out0 clkbaud8x key_entry2 } { 0.000ns 0.000ns 0.745ns 3.527ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.942 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns key_entry1 2 REG LC_X21_Y11_N0 4 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X21_Y11_N0; Fanout = 4; REG Node = 'key_entry1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.473 ns" { clk key_entry1 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 key_entry1 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.387 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.387 ns" { clk clk~out0 clkbaud8x key_entry2 } { 0.000ns 0.000ns 0.745ns 3.527ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 key_entry1 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.888 ns - Shortest register register " "Info: - Shortest register to register delay is 0.888 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_entry1 1 REG LC_X21_Y11_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y11_N0; Fanout = 4; REG Node = 'key_entry1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key_entry1 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.115 ns) 0.888 ns key_entry2 2 REG LC_X22_Y11_N7 19 " "Info: 2: + IC(0.773 ns) + CELL(0.115 ns) = 0.888 ns; Loc. = LC_X22_Y11_N7; Fanout = 19; REG Node = 'key_entry2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.888 ns" { key_entry1 key_entry2 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 12.95 % ) " "Info: Total cell delay = 0.115 ns ( 12.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns ( 87.05 % ) " "Info: Total interconnect delay = 0.773 ns ( 87.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.888 ns" { key_entry1 key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.888 ns" { key_entry1 key_entry2 } { 0.000ns 0.773ns } { 0.000ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.387 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.387 ns" { clk clk~out0 clkbaud8x key_entry2 } { 0.000ns 0.000ns 0.745ns 3.527ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 key_entry1 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.888 ns" { key_entry1 key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.888 ns" { key_entry1 key_entry2 } { 0.000ns 0.773ns } { 0.000ns 0.115ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "start_delaycnt key_input clk 7.486 ns register " "Info: tsu for register \"start_delaycnt\" (data pin = \"key_input\", clock pin = \"clk\") is 7.486 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.391 ns + Longest pin register " "Info: + Longest pin to register delay is 10.391 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns key_input 1 PIN PIN_105 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_105; Fanout = 2; PIN Node = 'key_input'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key_input } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.618 ns) + CELL(0.292 ns) 8.385 ns start_delaycnt~225 2 COMB LC_X21_Y11_N2 1 " "Info: 2: + IC(6.618 ns) + CELL(0.292 ns) = 8.385 ns; Loc. = LC_X21_Y11_N2; Fanout = 1; COMB Node = 'start_delaycnt~225'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.910 ns" { key_input start_delaycnt~225 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 8.681 ns start_delaycnt~226 3 COMB LC_X21_Y11_N3 1 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 8.681 ns; Loc. = LC_X21_Y11_N3; Fanout = 1; COMB Node = 'start_delaycnt~226'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { start_delaycnt~225 start_delaycnt~226 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.232 ns) + CELL(0.478 ns) 10.391 ns start_delaycnt 4 REG LC_X21_Y12_N7 21 " "Info: 4: + IC(1.232 ns) + CELL(0.478 ns) = 10.391 ns; Loc. = LC_X21_Y12_N7; Fanout = 21; REG Node = 'start_delaycnt'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.710 ns" { start_delaycnt~226 start_delaycnt } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.359 ns ( 22.70 % ) " "Info: Total cell delay = 2.359 ns ( 22.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.032 ns ( 77.30 % ) " "Info: Total interconnect delay = 8.032 ns ( 77.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.391 ns" { key_input start_delaycnt~225 start_delaycnt~226 start_delaycnt } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.391 ns" { key_input key_input~out0 start_delaycnt~225 start_delaycnt~226 start_delaycnt } { 0.000ns 0.000ns 6.618ns 0.182ns 1.232ns } { 0.000ns 1.475ns 0.292ns 0.114ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 53 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.942 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns start_delaycnt 2 REG LC_X21_Y12_N7 21 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X21_Y12_N7; Fanout = 21; REG Node = 'start_delaycnt'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.473 ns" { clk start_delaycnt } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk start_delaycnt } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 start_delaycnt } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.391 ns" { key_input start_delaycnt~225 start_delaycnt~226 start_delaycnt } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.391 ns" { key_input key_input~out0 start_delaycnt~225 start_delaycnt~226 start_delaycnt } { 0.000ns 0.000ns 6.618ns 0.182ns 1.232ns } { 0.000ns 1.475ns 0.292ns 0.114ns 0.478ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk start_delaycnt } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 start_delaycnt } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg_data\[7\] rxd_buf\[0\] 17.156 ns register " "Info: tco from clock \"clk\" to destination pin \"seg_data\[7\]\" through register \"rxd_buf\[0\]\" is 17.156 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.408 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.408 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clkbaud8x 2 REG LC_X8_Y10_N9 40 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N9; Fanout = 40; REG Node = 'clkbaud8x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk clkbaud8x } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.548 ns) + CELL(0.711 ns) 7.408 ns rxd_buf\[0\] 3 REG LC_X25_Y19_N1 9 " "Info: 3: + IC(3.548 ns) + CELL(0.711 ns) = 7.408 ns; Loc. = LC_X25_Y19_N1; Fanout = 9; REG Node = 'rxd_buf\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.259 ns" { clkbaud8x rxd_buf[0] } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 303 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.05 % ) " "Info: Total cell delay = 3.115 ns ( 42.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.293 ns ( 57.95 % ) " "Info: Total interconnect delay = 4.293 ns ( 57.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.408 ns" { clk clkbaud8x rxd_buf[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.408 ns" { clk clk~out0 clkbaud8x rxd_buf[0] } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 303 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.524 ns + Longest register pin " "Info: + Longest register to pin delay is 9.524 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rxd_buf\[0\] 1 REG LC_X25_Y19_N1 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y19_N1; Fanout = 9; REG Node = 'rxd_buf\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rxd_buf[0] } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 303 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.313 ns) + CELL(0.590 ns) 2.903 ns Mux23~620 2 COMB LC_X24_Y19_N4 1 " "Info: 2: + IC(2.313 ns) + CELL(0.590 ns) = 2.903 ns; Loc. = LC_X24_Y19_N4; Fanout = 1; COMB Node = 'Mux23~620'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.903 ns" { rxd_buf[0] Mux23~620 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 338 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.406 ns) + CELL(0.442 ns) 3.751 ns Mux23~622 3 COMB LC_X24_Y19_N6 1 " "Info: 3: + IC(0.406 ns) + CELL(0.442 ns) = 3.751 ns; Loc. = LC_X24_Y19_N6; Fanout = 1; COMB Node = 'Mux23~622'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.848 ns" { Mux23~620 Mux23~622 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 338 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.710 ns) + CELL(0.590 ns) 5.051 ns Mux23~623 4 COMB LC_X25_Y19_N3 1 " "Info: 4: + IC(0.710 ns) + CELL(0.590 ns) = 5.051 ns; Loc. = LC_X25_Y19_N3; Fanout = 1; COMB Node = 'Mux23~623'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { Mux23~622 Mux23~623 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 338 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.365 ns) + CELL(2.108 ns) 9.524 ns seg_data\[7\] 5 PIN PIN_215 0 " "Info: 5: + IC(2.365 ns) + CELL(2.108 ns) = 9.524 ns; Loc. = PIN_215; Fanout = 0; PIN Node = 'seg_data\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.473 ns" { Mux23~623 seg_data[7] } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.730 ns ( 39.16 % ) " "Info: Total cell delay = 3.730 ns ( 39.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.794 ns ( 60.84 % ) " "Info: Total interconnect delay = 5.794 ns ( 60.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.524 ns" { rxd_buf[0] Mux23~620 Mux23~622 Mux23~623 seg_data[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.524 ns" { rxd_buf[0] Mux23~620 Mux23~622 Mux23~623 seg_data[7] } { 0.000ns 2.313ns 0.406ns 0.710ns 2.365ns } { 0.000ns 0.590ns 0.442ns 0.590ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.408 ns" { clk clkbaud8x rxd_buf[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.408 ns" { clk clk~out0 clkbaud8x rxd_buf[0] } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.524 ns" { rxd_buf[0] Mux23~620 Mux23~622 Mux23~623 seg_data[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.524 ns" { rxd_buf[0] Mux23~620 Mux23~622 Mux23~623 seg_data[7] } { 0.000ns 2.313ns 0.406ns 0.710ns 2.365ns } { 0.000ns 0.590ns 0.442ns 0.590ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
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