uartt.map.qmsg

串口程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 16 17:35:00 2007 " "Info: Processing started: Thu Aug 16 17:35:00 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off uartt -c uartt " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uartt -c uartt" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "appl.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file appl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 appl-SYN " "Info: Found design unit 1: appl-SYN" {  } { { "appl.vhd" "" { Text "D:/altera/quartus60/program/UART/appl.vhd" 48 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 appl " "Info: Found entity 1: appl" {  } { { "appl.vhd" "" { Text "D:/altera/quartus60/program/UART/appl.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fenpin.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fenpin.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenpin-arch " "Info: Found design unit 1: fenpin-arch" {  } { { "fenpin.vhd" "" { Text "D:/altera/quartus60/program/UART/fenpin.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fenpin " "Info: Found entity 1: fenpin" {  } { { "fenpin.vhd" "" { Text "D:/altera/quartus60/program/UART/fenpin.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UART.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file UART.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UART-arch " "Info: Found design unit 1: UART-arch" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 31 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 UART " "Info: Found entity 1: UART" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 19 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uartt.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file uartt.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 uartt " "Info: Found entity 1: uartt" {  } { { "uartt.bdf" "" { Schematic "D:/altera/quartus60/program/UART/uartt.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "uartt " "Info: Elaborating entity \"uartt\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UART UART:inst " "Info: Elaborating entity \"UART\" for hierarchy \"UART:inst\"" {  } { { "uartt.bdf" "inst" { Schematic "D:/altera/quartus60/program/UART/uartt.bdf" { { 240 616 792 368 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "appl appl:inst1 " "Info: Elaborating entity \"appl\" for hierarchy \"appl:inst1\"" {  } { { "uartt.bdf" "inst1" { Schematic "D:/altera/quartus60/program/UART/uartt.bdf" { { 72 240 480 232 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 365 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll appl:inst1\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"appl:inst1\|altpll:altpll_component\"" {  } { { "appl.vhd" "altpll_component" { Text "D:/altera/quartus60/program/UART/appl.vhd" 127 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "appl:inst1\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"appl:inst1\|altpll:altpll_component\"" {  } { { "appl.vhd" "" { Text "D:/altera/quartus60/program/UART/appl.vhd" 127 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "UART:inst\|txd_buf\[7\] data_in GND " "Warning: Reduced register \"UART:inst\|txd_buf\[7\]\" with stuck data_in port to stuck value GND" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 183 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "en GND " "Warning: Pin \"en\" stuck at GND" {  } { { "uartt.bdf" "" { Schematic "D:/altera/quartus60/program/UART/uartt.bdf" { { 280 800 976 296 "en" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "seg_out\[0\] VCC " "Warning: Pin \"seg_out\[0\]\" stuck at VCC" {  } { { "uartt.bdf" "" { Schematic "D:/altera/quartus60/program/UART/uartt.bdf" { { 296 840 1016 312 "seg_out\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 183 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "223 " "Info: Implemented 223 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "208 " "Info: Implemented 208 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 16 17:35:07 2007 " "Info: Processing ended: Thu Aug 16 17:35:07 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}