uart.fit.qmsg

串口程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 16 16:58:02 2007 " "Info: Processing started: Thu Aug 16 16:58:02 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off UART -c UART " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off UART -c UART" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "UART EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"UART\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IMPP_MPP_DEV_MIG_DEVICE_LIST_MESSAGE_TOP" "" "Info: Selected Migration Device List" { { "Info" "IMPP_MPP_DEV_MIG_DEVICE_LIST_MESSAGE_SUB" "EP1C12Q240C8 " "Info: Selected EP1C12Q240C8 for migration" {  } {  } 0 0 "Selected %1!s! for migration" 0 0}  } {  } 0 0 "Selected Migration Device List" 0 0}
{ "Info" "IMPP_MPP_NUM_MIGRATABLE_IO" "227 " "Info: Selected migration device list is legal with 227 total of migratable pins" {  } {  } 0 0 "Selected migration device list is legal with %1!d! total of migratable pins" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "ICUT_CUT_MIGRATION_PIN_IMPLEMENTED_AS_TRISTATED_INPUT" "6 " "Info: Selected device migration path implemented 6 pin(s) as tristated input(s)" { { "Info" "ICUT_CUT_MIGRATION_PIN_NAME_SUB" "81 " "Info: Pin \"81\"" {  } {  } 0 0 "Pin \"%1!s!\"" 0 0} { "Info" "ICUT_CUT_MIGRATION_PIN_NAME_SUB" "97 " "Info: Pin \"97\"" {  } {  } 0 0 "Pin \"%1!s!\"" 0 0} { "Info" "ICUT_CUT_MIGRATION_PIN_NAME_SUB" "103 " "Info: Pin \"103\"" {  } {  } 0 0 "Pin \"%1!s!\"" 0 0} { "Info" "ICUT_CUT_MIGRATION_PIN_NAME_SUB" "198 " "Info: Pin \"198\"" {  } {  } 0 0 "Pin \"%1!s!\"" 0 0} { "Info" "ICUT_CUT_MIGRATION_PIN_NAME_SUB" "204 " "Info: Pin \"204\"" {  } {  } 0 0 "Pin \"%1!s!\"" 0 0} { "Info" "ICUT_CUT_MIGRATION_PIN_NAME_SUB" "220 " "Info: Pin \"220\"" {  } {  } 0 0 "Pin \"%1!s!\"" 0 0}  } {  } 0 0 "Selected device migration path implemented %1!d! pin(s) as tristated input(s)" 0 0}
{ "Info" "ICUT_CUT_MIGRATION_PIN_IMPLEMENTED_AS_GND" "6 " "Info: Selected device migration path implemented 6 pin(s) as GND" { { "Info" "ICUT_CUT_MIGRATION_PIN_NAME_SUB" "80 " "Info: Pin \"80\"" {  } {  } 0 0 "Pin \"%1!s!\"" 0 0} { "Info" "ICUT_CUT_MIGRATION_PIN_NAME_SUB" "96 " "Info: Pin \"96\"" {  } {  } 0 0 "Pin \"%1!s!\"" 0 0} { "Info" "ICUT_CUT_MIGRATION_PIN_NAME_SUB" "102 " "Info: Pin \"102\"" {  } {  } 0 0 "Pin \"%1!s!\"" 0 0} { "Info" "ICUT_CUT_MIGRATION_PIN_NAME_SUB" "199 " "Info: Pin \"199\"" {  } {  } 0 0 "Pin \"%1!s!\"" 0 0} { "Info" "ICUT_CUT_MIGRATION_PIN_NAME_SUB" "205 " "Info: Pin \"205\"" {  } {  } 0 0 "Pin \"%1!s!\"" 0 0} { "Info" "ICUT_CUT_MIGRATION_PIN_NAME_SUB" "221 " "Info: Pin \"221\"" {  } {  } 0 0 "Pin \"%1!s!\"" 0 0}  } {  } 0 0 "Selected device migration path implemented %1!d! pin(s) as GND" 0 0}
{ "Info" "IFYGR_FYGR_MIGRATION_PIN_CANNOT_BE_USED_AS" "12 regular " "Info: Selected device migration path cannot use 12 pins as \"regular\" I/Os" { { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "80 " "Info: Pin \"80\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "81 " "Info: Pin \"81\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "96 " "Info: Pin \"96\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "97 " "Info: Pin \"97\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "102 " "Info: Pin \"102\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "103 " "Info: Pin \"103\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "198 " "Info: Pin \"198\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "199 " "Info: Pin \"199\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "204 " "Info: Pin \"204\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "205 " "Info: Pin \"205\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "220 " "Info: Pin \"220\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0} { "Info" "IFYGR_FYGR_MIGRATION_PIN_NAME_SUB" "221 " "Info: Pin \"221\"" {  } {  } 2 0 "Pin \"%1!s!\"" 0 0}  } {  } 2 0 "Selected device migration path cannot use %1!d! pins as \"%2!s!\" I/Os" 0 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 29 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 29" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 21 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clkbaud8x Global clock " "Info: Automatically promoted some destinations of signal \"clkbaud8x\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clkbaud8x " "Info: Destination \"clkbaud8x\" may be non-global or may not use global clock" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 42 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 42 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rst Global clock " "Info: Automatically promoted signal \"rst\" to use Global clock" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 22 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rst " "Info: Pin \"rst\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 22 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "rst" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}