uartt.tan.qmsg

串口程序

{ "Info" "ITDB_TH_RESULT" "UART:inst\|rxd_reg1 din clk -4.458 ns register " "Info: th for register \"UART:inst\|rxd_reg1\" (data pin = \"din\", clock pin = \"clk\") is -4.458 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk appl:inst1\|altpll:altpll_component\|_clk0 -2.054 ns + " "Info: + Offset between input clock \"clk\" and output clock \"appl:inst1\|altpll:altpll_component\|_clk0\" is -2.054 ns" {  } { { "uartt.bdf" "" { Schematic "D:/altera/quartus60/program/UART/uartt.bdf" { { 128 0 168 144 "clk" "" } } } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "appl:inst1\|altpll:altpll_component\|_clk0 destination 6.936 ns + Longest register " "Info: + Longest clock path from clock \"appl:inst1\|altpll:altpll_component\|_clk0\" to destination register is 6.936 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns appl:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 39; CLK Node = 'appl:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { appl:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns UART:inst\|clkbaud8x 2 REG LC_X8_Y13_N2 40 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X8_Y13_N2; Fanout = 40; REG Node = 'UART:inst\|clkbaud8x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.713 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.512 ns) + CELL(0.711 ns) 6.936 ns UART:inst\|rxd_reg1 3 REG LC_X39_Y10_N3 2 " "Info: 3: + IC(3.512 ns) + CELL(0.711 ns) = 6.936 ns; Loc. = LC_X39_Y10_N3; Fanout = 2; REG Node = 'UART:inst\|rxd_reg1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.223 ns" { UART:inst|clkbaud8x UART:inst|rxd_reg1 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 23.73 % ) " "Info: Total cell delay = 1.646 ns ( 23.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.290 ns ( 76.27 % ) " "Info: Total interconnect delay = 5.290 ns ( 76.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.936 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|rxd_reg1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.936 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|rxd_reg1 } { 0.000ns 1.778ns 3.512ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 46 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.355 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.355 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns din 1 PIN PIN_179 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_179; Fanout = 1; PIN Node = 'din'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { din } "NODE_NAME" } } { "uartt.bdf" "" { Schematic "D:/altera/quartus60/program/UART/uartt.bdf" { { 296 400 568 312 "din" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.771 ns) + CELL(0.115 ns) 9.355 ns UART:inst\|rxd_reg1 2 REG LC_X39_Y10_N3 2 " "Info: 2: + IC(7.771 ns) + CELL(0.115 ns) = 9.355 ns; Loc. = LC_X39_Y10_N3; Fanout = 2; REG Node = 'UART:inst\|rxd_reg1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.886 ns" { din UART:inst|rxd_reg1 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 16.93 % ) " "Info: Total cell delay = 1.584 ns ( 16.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.771 ns ( 83.07 % ) " "Info: Total interconnect delay = 7.771 ns ( 83.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.355 ns" { din UART:inst|rxd_reg1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.355 ns" { din din~out0 UART:inst|rxd_reg1 } { 0.000ns 0.000ns 7.771ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.936 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|rxd_reg1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.936 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|rxd_reg1 } { 0.000ns 1.778ns 3.512ns } { 0.000ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.355 ns" { din UART:inst|rxd_reg1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.355 ns" { din din~out0 UART:inst|rxd_reg1 } { 0.000ns 0.000ns 7.771ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Critical Warning" "WTAN_REQUIREMENTS_NOT_MET" "" "Critical Warning: Timing requirements were not met. See Report window for details." {  } {  } 1 0 "Timing requirements were not met. See Report window for details." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 16 17:35:29 2007 " "Info: Processing ended: Thu Aug 16 17:35:29 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}