uartt.tan.qmsg

串口程序

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "appl:inst1\|altpll:altpll_component\|_clk0 register UART:inst\|key_entry1 register UART:inst\|key_entry2 -2.643 ns " "Info: Minimum slack time is -2.643 ns for clock \"appl:inst1\|altpll:altpll_component\|_clk0\" between source register \"UART:inst\|key_entry1\" and destination register \"UART:inst\|key_entry2\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.697 ns + Shortest register register " "Info: + Shortest register to register delay is 1.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns UART:inst\|key_entry1 1 REG LC_X13_Y12_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y12_N5; Fanout = 4; REG Node = 'UART:inst\|key_entry1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { UART:inst|key_entry1 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.582 ns) + CELL(0.115 ns) 1.697 ns UART:inst\|key_entry2 2 REG LC_X18_Y12_N8 19 " "Info: 2: + IC(1.582 ns) + CELL(0.115 ns) = 1.697 ns; Loc. = LC_X18_Y12_N8; Fanout = 19; REG Node = 'UART:inst\|key_entry2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.697 ns" { UART:inst|key_entry1 UART:inst|key_entry2 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 6.78 % ) " "Info: Total cell delay = 0.115 ns ( 6.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.582 ns ( 93.22 % ) " "Info: Total interconnect delay = 1.582 ns ( 93.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.697 ns" { UART:inst|key_entry1 UART:inst|key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.697 ns" { UART:inst|key_entry1 UART:inst|key_entry2 } { 0.000ns 1.582ns } { 0.000ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "4.340 ns - Smallest register register " "Info: - Smallest register to register requirement is 4.340 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.054 ns " "Info: + Latch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination appl:inst1\|altpll:altpll_component\|_clk0 41.666 ns -2.054 ns  50 " "Info: Clock period of Destination clock \"appl:inst1\|altpll:altpll_component\|_clk0\" is 41.666 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.054 ns " "Info: - Launch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source appl:inst1\|altpll:altpll_component\|_clk0 41.666 ns -2.054 ns  50 " "Info: Clock period of Source clock \"appl:inst1\|altpll:altpll_component\|_clk0\" is 41.666 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.549 ns + Smallest " "Info: + Smallest clock skew is 4.549 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "appl:inst1\|altpll:altpll_component\|_clk0 destination 6.997 ns + Longest register " "Info: + Longest clock path from clock \"appl:inst1\|altpll:altpll_component\|_clk0\" to destination register is 6.997 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns appl:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 39; CLK Node = 'appl:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { appl:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns UART:inst\|clkbaud8x 2 REG LC_X8_Y13_N2 40 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X8_Y13_N2; Fanout = 40; REG Node = 'UART:inst\|clkbaud8x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.713 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.573 ns) + CELL(0.711 ns) 6.997 ns UART:inst\|key_entry2 3 REG LC_X18_Y12_N8 19 " "Info: 3: + IC(3.573 ns) + CELL(0.711 ns) = 6.997 ns; Loc. = LC_X18_Y12_N8; Fanout = 19; REG Node = 'UART:inst\|key_entry2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.284 ns" { UART:inst|clkbaud8x UART:inst|key_entry2 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 23.52 % ) " "Info: Total cell delay = 1.646 ns ( 23.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.351 ns ( 76.48 % ) " "Info: Total interconnect delay = 5.351 ns ( 76.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.997 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.997 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|key_entry2 } { 0.000ns 1.778ns 3.573ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "appl:inst1\|altpll:altpll_component\|_clk0 source 2.448 ns - Shortest register " "Info: - Shortest clock path from clock \"appl:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.448 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns appl:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 39; CLK Node = 'appl:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { appl:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.737 ns) + CELL(0.711 ns) 2.448 ns UART:inst\|key_entry1 2 REG LC_X13_Y12_N5 4 " "Info: 2: + IC(1.737 ns) + CELL(0.711 ns) = 2.448 ns; Loc. = LC_X13_Y12_N5; Fanout = 4; REG Node = 'UART:inst\|key_entry1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.04 % ) " "Info: Total cell delay = 0.711 ns ( 29.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.737 ns ( 70.96 % ) " "Info: Total interconnect delay = 1.737 ns ( 70.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } { 0.000ns 1.737ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.997 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.997 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|key_entry2 } { 0.000ns 1.778ns 3.573ns } { 0.000ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } { 0.000ns 1.737ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.997 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.997 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|key_entry2 } { 0.000ns 1.778ns 3.573ns } { 0.000ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } { 0.000ns 1.737ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.697 ns" { UART:inst|key_entry1 UART:inst|key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.697 ns" { UART:inst|key_entry1 UART:inst|key_entry2 } { 0.000ns 1.582ns } { 0.000ns 0.115ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.997 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.997 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|key_entry2 } { 0.000ns 1.778ns 3.573ns } { 0.000ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } { 0.000ns 1.737ns } { 0.000ns 0.711ns } } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_FULL_MINIMUM_REQUIREMENTS_NOT_MET" "appl:inst1\|altpll:altpll_component\|_clk0 8 " "Warning: Can't achieve minimum setup and hold requirement appl:inst1\|altpll:altpll_component\|_clk0 along 8 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve minimum setup and hold requirement %1!s! along %2!d! path(s). See Report window for details." 0 0}
{ "Info" "ITDB_TSU_RESULT" "UART:inst\|start_delaycnt skp clk 10.568 ns register " "Info: tsu for register \"UART:inst\|start_delaycnt\" (data pin = \"skp\", clock pin = \"clk\") is 10.568 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.925 ns + Longest pin register " "Info: + Longest pin to register delay is 10.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns skp 1 PIN PIN_235 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_235; Fanout = 2; PIN Node = 'skp'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { skp } "NODE_NAME" } } { "uartt.bdf" "" { Schematic "D:/altera/quartus60/program/UART/uartt.bdf" { { 312 392 560 328 "skp" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.064 ns) + CELL(0.292 ns) 8.831 ns UART:inst\|start_delaycnt~225 2 COMB LC_X13_Y11_N2 1 " "Info: 2: + IC(7.064 ns) + CELL(0.292 ns) = 8.831 ns; Loc. = LC_X13_Y11_N2; Fanout = 1; COMB Node = 'UART:inst\|start_delaycnt~225'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.356 ns" { skp UART:inst|start_delaycnt~225 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 9.127 ns UART:inst\|start_delaycnt~226 3 COMB LC_X13_Y11_N3 1 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 9.127 ns; Loc. = LC_X13_Y11_N3; Fanout = 1; COMB Node = 'UART:inst\|start_delaycnt~226'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { UART:inst|start_delaycnt~225 UART:inst|start_delaycnt~226 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.191 ns) + CELL(0.607 ns) 10.925 ns UART:inst\|start_delaycnt 4 REG LC_X13_Y12_N4 21 " "Info: 4: + IC(1.191 ns) + CELL(0.607 ns) = 10.925 ns; Loc. = LC_X13_Y12_N4; Fanout = 21; REG Node = 'UART:inst\|start_delaycnt'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.798 ns" { UART:inst|start_delaycnt~226 UART:inst|start_delaycnt } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.488 ns ( 22.77 % ) " "Info: Total cell delay = 2.488 ns ( 22.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.437 ns ( 77.23 % ) " "Info: Total interconnect delay = 8.437 ns ( 77.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.925 ns" { skp UART:inst|start_delaycnt~225 UART:inst|start_delaycnt~226 UART:inst|start_delaycnt } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.925 ns" { skp skp~out0 UART:inst|start_delaycnt~225 UART:inst|start_delaycnt~226 UART:inst|start_delaycnt } { 0.000ns 0.000ns 7.064ns 0.182ns 1.191ns } { 0.000ns 1.475ns 0.292ns 0.114ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 53 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_PLL_OFFSET" "clk appl:inst1\|altpll:altpll_component\|_clk0 -2.054 ns - " "Info: - Offset between input clock \"clk\" and output clock \"appl:inst1\|altpll:altpll_component\|_clk0\" is -2.054 ns" {  } { { "uartt.bdf" "" { Schematic "D:/altera/quartus60/program/UART/uartt.bdf" { { 128 0 168 144 "clk" "" } } } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "appl:inst1\|altpll:altpll_component\|_clk0 destination 2.448 ns - Shortest register " "Info: - Shortest clock path from clock \"appl:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.448 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns appl:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 39; CLK Node = 'appl:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { appl:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.737 ns) + CELL(0.711 ns) 2.448 ns UART:inst\|start_delaycnt 2 REG LC_X13_Y12_N4 21 " "Info: 2: + IC(1.737 ns) + CELL(0.711 ns) = 2.448 ns; Loc. = LC_X13_Y12_N4; Fanout = 21; REG Node = 'UART:inst\|start_delaycnt'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|start_delaycnt } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.04 % ) " "Info: Total cell delay = 0.711 ns ( 29.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.737 ns ( 70.96 % ) " "Info: Total interconnect delay = 1.737 ns ( 70.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|start_delaycnt } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|start_delaycnt } { 0.000ns 1.737ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.925 ns" { skp UART:inst|start_delaycnt~225 UART:inst|start_delaycnt~226 UART:inst|start_delaycnt } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.925 ns" { skp skp~out0 UART:inst|start_delaycnt~225 UART:inst|start_delaycnt~226 UART:inst|start_delaycnt } { 0.000ns 0.000ns 7.064ns 0.182ns 1.191ns } { 0.000ns 1.475ns 0.292ns 0.114ns 0.607ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|start_delaycnt } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|start_delaycnt } { 0.000ns 1.737ns } { 0.000ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg_out\[2\] UART:inst\|rxd_buf\[1\] 15.523 ns register " "Info: tco from clock \"clk\" to destination pin \"seg_out\[2\]\" through register \"UART:inst\|rxd_buf\[1\]\" is 15.523 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk appl:inst1\|altpll:altpll_component\|_clk0 -2.054 ns + " "Info: + Offset between input clock \"clk\" and output clock \"appl:inst1\|altpll:altpll_component\|_clk0\" is -2.054 ns" {  } { { "uartt.bdf" "" { Schematic "D:/altera/quartus60/program/UART/uartt.bdf" { { 128 0 168 144 "clk" "" } } } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "appl:inst1\|altpll:altpll_component\|_clk0 source 6.999 ns + Longest register " "Info: + Longest clock path from clock \"appl:inst1\|altpll:altpll_component\|_clk0\" to source register is 6.999 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns appl:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 39; CLK Node = 'appl:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { appl:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns UART:inst\|clkbaud8x 2 REG LC_X8_Y13_N2 40 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X8_Y13_N2; Fanout = 40; REG Node = 'UART:inst\|clkbaud8x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.713 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.575 ns) + CELL(0.711 ns) 6.999 ns UART:inst\|rxd_buf\[1\] 3 REG LC_X40_Y14_N3 10 " "Info: 3: + IC(3.575 ns) + CELL(0.711 ns) = 6.999 ns; Loc. = LC_X40_Y14_N3; Fanout = 10; REG Node = 'UART:inst\|rxd_buf\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.286 ns" { UART:inst|clkbaud8x UART:inst|rxd_buf[1] } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 303 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 23.52 % ) " "Info: Total cell delay = 1.646 ns ( 23.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.353 ns ( 76.48 % ) " "Info: Total interconnect delay = 5.353 ns ( 76.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.999 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|rxd_buf[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.999 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|rxd_buf[1] } { 0.000ns 1.778ns 3.575ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 303 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.354 ns + Longest register pin " "Info: + Longest register to pin delay is 10.354 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns UART:inst\|rxd_buf\[1\] 1 REG LC_X40_Y14_N3 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X40_Y14_N3; Fanout = 10; REG Node = 'UART:inst\|rxd_buf\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { UART:inst|rxd_buf[1] } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 303 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.844 ns) + CELL(0.442 ns) 1.286 ns UART:inst\|Mux27~875 2 COMB LC_X40_Y14_N7 1 " "Info: 2: + IC(0.844 ns) + CELL(0.442 ns) = 1.286 ns; Loc. = LC_X40_Y14_N7; Fanout = 1; COMB Node = 'UART:inst\|Mux27~875'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.286 ns" { UART:inst|rxd_buf[1] UART:inst|Mux27~875 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 338 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.088 ns) + CELL(0.114 ns) 2.488 ns UART:inst\|Mux23~713 3 COMB LC_X40_Y14_N6 4 " "Info: 3: + IC(1.088 ns) + CELL(0.114 ns) = 2.488 ns; Loc. = LC_X40_Y14_N6; Fanout = 4; COMB Node = 'UART:inst\|Mux23~713'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.202 ns" { UART:inst|Mux27~875 UART:inst|Mux23~713 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 338 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.106 ns) + CELL(0.114 ns) 3.708 ns UART:inst\|Mux29~620 4 COMB LC_X40_Y14_N8 4 " "Info: 4: + IC(1.106 ns) + CELL(0.114 ns) = 3.708 ns; Loc. = LC_X40_Y14_N8; Fanout = 4; COMB Node = 'UART:inst\|Mux29~620'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.220 ns" { UART:inst|Mux23~713 UART:inst|Mux29~620 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 338 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.088 ns) + CELL(0.442 ns) 5.238 ns UART:inst\|Mux28~630 5 COMB LC_X42_Y14_N3 1 " "Info: 5: + IC(1.088 ns) + CELL(0.442 ns) = 5.238 ns; Loc. = LC_X42_Y14_N3; Fanout = 1; COMB Node = 'UART:inst\|Mux28~630'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.530 ns" { UART:inst|Mux29~620 UART:inst|Mux28~630 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 338 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.008 ns) + CELL(2.108 ns) 10.354 ns seg_out\[2\] 6 PIN PIN_193 0 " "Info: 6: + IC(3.008 ns) + CELL(2.108 ns) = 10.354 ns; Loc. = PIN_193; Fanout = 0; PIN Node = 'seg_out\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.116 ns" { UART:inst|Mux28~630 seg_out[2] } "NODE_NAME" } } { "uartt.bdf" "" { Schematic "D:/altera/quartus60/program/UART/uartt.bdf" { { 296 840 1016 312 "seg_out\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.220 ns ( 31.10 % ) " "Info: Total cell delay = 3.220 ns ( 31.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.134 ns ( 68.90 % ) " "Info: Total interconnect delay = 7.134 ns ( 68.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.354 ns" { UART:inst|rxd_buf[1] UART:inst|Mux27~875 UART:inst|Mux23~713 UART:inst|Mux29~620 UART:inst|Mux28~630 seg_out[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.354 ns" { UART:inst|rxd_buf[1] UART:inst|Mux27~875 UART:inst|Mux23~713 UART:inst|Mux29~620 UART:inst|Mux28~630 seg_out[2] } { 0.000ns 0.844ns 1.088ns 1.106ns 1.088ns 3.008ns } { 0.000ns 0.442ns 0.114ns 0.114ns 0.442ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.999 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|rxd_buf[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.999 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|rxd_buf[1] } { 0.000ns 1.778ns 3.575ns } { 0.000ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.354 ns" { UART:inst|rxd_buf[1] UART:inst|Mux27~875 UART:inst|Mux23~713 UART:inst|Mux29~620 UART:inst|Mux28~630 seg_out[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.354 ns" { UART:inst|rxd_buf[1] UART:inst|Mux27~875 UART:inst|Mux23~713 UART:inst|Mux29~620 UART:inst|Mux28~630 seg_out[2] } { 0.000ns 0.844ns 1.088ns 1.106ns 1.088ns 3.008ns } { 0.000ns 0.442ns 0.114ns 0.114ns 0.442ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}