uartt.tan.qmsg

串口程序

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "UART:inst\|clkbaud8x " "Info: Detected ripple clock \"UART:inst\|clkbaud8x\" as buffer" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 42 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "UART:inst\|clkbaud8x" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "appl:inst1\|altpll:altpll_component\|_clk0 register UART:inst\|key_entry2 register UART:inst\|key_entry1 34.165 ns " "Info: Slack time is 34.165 ns for clock \"appl:inst1\|altpll:altpll_component\|_clk0\" between source register \"UART:inst\|key_entry2\" and destination register \"UART:inst\|key_entry1\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "133.32 MHz 7.501 ns " "Info: Fmax is 133.32 MHz (period= 7.501 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "36.856 ns + Largest register register " "Info: + Largest register to register requirement is 36.856 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "41.666 ns + " "Info: + Setup relationship between source and destination is 41.666 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 39.612 ns " "Info: + Latch edge is 39.612 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination appl:inst1\|altpll:altpll_component\|_clk0 41.666 ns -2.054 ns  50 " "Info: Clock period of Destination clock \"appl:inst1\|altpll:altpll_component\|_clk0\" is 41.666 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.054 ns " "Info: - Launch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source appl:inst1\|altpll:altpll_component\|_clk0 41.666 ns -2.054 ns  50 " "Info: Clock period of Source clock \"appl:inst1\|altpll:altpll_component\|_clk0\" is 41.666 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.549 ns + Largest " "Info: + Largest clock skew is -4.549 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "appl:inst1\|altpll:altpll_component\|_clk0 destination 2.448 ns + Shortest register " "Info: + Shortest clock path from clock \"appl:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.448 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns appl:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 39; CLK Node = 'appl:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { appl:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.737 ns) + CELL(0.711 ns) 2.448 ns UART:inst\|key_entry1 2 REG LC_X13_Y12_N5 4 " "Info: 2: + IC(1.737 ns) + CELL(0.711 ns) = 2.448 ns; Loc. = LC_X13_Y12_N5; Fanout = 4; REG Node = 'UART:inst\|key_entry1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.04 % ) " "Info: Total cell delay = 0.711 ns ( 29.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.737 ns ( 70.96 % ) " "Info: Total interconnect delay = 1.737 ns ( 70.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } { 0.000ns 1.737ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "appl:inst1\|altpll:altpll_component\|_clk0 source 6.997 ns - Longest register " "Info: - Longest clock path from clock \"appl:inst1\|altpll:altpll_component\|_clk0\" to source register is 6.997 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns appl:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 39; CLK Node = 'appl:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { appl:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns UART:inst\|clkbaud8x 2 REG LC_X8_Y13_N2 40 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X8_Y13_N2; Fanout = 40; REG Node = 'UART:inst\|clkbaud8x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.713 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.573 ns) + CELL(0.711 ns) 6.997 ns UART:inst\|key_entry2 3 REG LC_X18_Y12_N8 19 " "Info: 3: + IC(3.573 ns) + CELL(0.711 ns) = 6.997 ns; Loc. = LC_X18_Y12_N8; Fanout = 19; REG Node = 'UART:inst\|key_entry2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.284 ns" { UART:inst|clkbaud8x UART:inst|key_entry2 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 23.52 % ) " "Info: Total cell delay = 1.646 ns ( 23.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.351 ns ( 76.48 % ) " "Info: Total interconnect delay = 5.351 ns ( 76.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.997 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.997 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|key_entry2 } { 0.000ns 1.778ns 3.573ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } { 0.000ns 1.737ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.997 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.997 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|key_entry2 } { 0.000ns 1.778ns 3.573ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } { 0.000ns 1.737ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.997 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.997 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|key_entry2 } { 0.000ns 1.778ns 3.573ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.691 ns - Longest register register " "Info: - Longest register to register delay is 2.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns UART:inst\|key_entry2 1 REG LC_X18_Y12_N8 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y12_N8; Fanout = 19; REG Node = 'UART:inst\|key_entry2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { UART:inst|key_entry2 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.579 ns) + CELL(1.112 ns) 2.691 ns UART:inst\|key_entry1 2 REG LC_X13_Y12_N5 4 " "Info: 2: + IC(1.579 ns) + CELL(1.112 ns) = 2.691 ns; Loc. = LC_X13_Y12_N5; Fanout = 4; REG Node = 'UART:inst\|key_entry1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { UART:inst|key_entry2 UART:inst|key_entry1 } "NODE_NAME" } } { "UART.vhd" "" { Text "D:/altera/quartus60/program/UART/UART.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.112 ns ( 41.32 % ) " "Info: Total cell delay = 1.112 ns ( 41.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.579 ns ( 58.68 % ) " "Info: Total interconnect delay = 1.579 ns ( 58.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { UART:inst|key_entry2 UART:inst|key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { UART:inst|key_entry2 UART:inst|key_entry1 } { 0.000ns 1.579ns } { 0.000ns 1.112ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|key_entry1 } { 0.000ns 1.737ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.997 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|key_entry2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.997 ns" { appl:inst1|altpll:altpll_component|_clk0 UART:inst|clkbaud8x UART:inst|key_entry2 } { 0.000ns 1.778ns 3.573ns } { 0.000ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { UART:inst|key_entry2 UART:inst|key_entry1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { UART:inst|key_entry2 UART:inst|key_entry1 } { 0.000ns 1.579ns } { 0.000ns 1.112ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}