fenpin.vhd

来自「串口程序」· VHDL 代码 · 共 25 行

--通用分频器
library ieee;
use ieee.std_logic_1164.all;
entity fenpin is
  port(clock:in std_logic;
       clko:out std_logic
       );
  end fenpin;
architecture arch of fenpin is
 signal clk2:std_logic;
 signal cou:integer range 0 to 499999;
 begin
  process(clock)
 begin
  if(clock'event and clock='1') then
    if(cou=499999) then
     clk2<=not clk2;
    cou<=0;
  else cou<=cou+1;
  end if;
 end if;
end process;
clko<=clk2;
end arch;